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    <title>topic PRI backplane clock source in Routing and SD-WAN</title>
    <link>https://community.cisco.com/t5/routing-and-sd-wan/pri-backplane-clock-source/m-p/1753967#M171533</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Ronit, one quick question, whether the command "network-clock-select 1 e1 0/0/0" will reset the PRIs? This is the besiness hrs for us.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 10 Oct 2011 12:04:56 GMT</pubDate>
    <dc:creator>Muralidharan.p</dc:creator>
    <dc:date>2011-10-10T12:04:56Z</dc:date>
    <item>
      <title>PRI backplane clock source</title>
      <link>https://community.cisco.com/t5/routing-and-sd-wan/pri-backplane-clock-source/m-p/1753962#M171528</link>
      <description>&lt;P&gt;Hi All,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We are having 2 PRI controllers, Slip sec in both the controllers are keep on increasing. The clock source is configured as "line", show network-clock showing the clock source as backplane. I dont know what is backplane clock soure and&amp;nbsp; i dont know which one is the primary controller for clock soure. Below are the ouput for your reference. I guess the configuration is not completed for clock source. Please advise. Thanks in advance.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;E1 0/0/0 is up.&lt;/P&gt;&lt;P&gt;&amp;nbsp; Applique type is Channelized E1 - balanced&lt;/P&gt;&lt;P&gt;&amp;nbsp; No alarms detected.&lt;/P&gt;&lt;P&gt;&amp;nbsp; alarm-trigger is not set&lt;/P&gt;&lt;P&gt;&amp;nbsp; Version info Firmware: 20100222, FPGA: 13, spm_count = 0&lt;/P&gt;&lt;P&gt;&amp;nbsp; Framing is CRC4, Line Code is HDB3, Clock Source is Line.&lt;/P&gt;&lt;P&gt;&amp;nbsp; Data in current interval (752 seconds elapsed):&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0 Line Code Violations, 0 Path Code Violations&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 16 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 16 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs&lt;/P&gt;&lt;P&gt;&amp;nbsp; Total Data (last 24 hours)&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0 Line Code Violations, 0 Path Code Violations,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 1816 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 1816 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;E1 0/0/1 is up.&lt;/P&gt;&lt;P&gt;&amp;nbsp; Applique type is Channelized E1 - balanced&lt;/P&gt;&lt;P&gt;&amp;nbsp; No alarms detected.&lt;/P&gt;&lt;P&gt;&amp;nbsp; alarm-trigger is not set&lt;/P&gt;&lt;P&gt;&amp;nbsp; Version info Firmware: 20100222, FPGA: 13, spm_count = 0&lt;/P&gt;&lt;P&gt;&amp;nbsp; Framing is CRC4, Line Code is HDB3, Clock Source is Line.&lt;/P&gt;&lt;P&gt;&amp;nbsp; Data in current interval (755 seconds elapsed):&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0 Line Code Violations, 0 Path Code Violations&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 16 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 16 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs&lt;/P&gt;&lt;P&gt;&amp;nbsp; Total Data (last 24 hours)&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0 Line Code Violations, 0 Path Code Violations,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 1816 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 1816 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs&lt;/P&gt;&lt;P&gt;-------------------------------------------------------&lt;/P&gt;&lt;P&gt;controller E1 0/0/0&lt;BR /&gt;pri-group timeslots 1-31 service mgcp&lt;BR /&gt;!&lt;BR /&gt;controller E1 0/0/1&lt;BR /&gt;pri-group timeslots 1-31 service mgcp&lt;/P&gt;&lt;P&gt;!&lt;/P&gt;&lt;P&gt;-----------------------------------------------------&lt;/P&gt;&lt;P&gt;&amp;nbsp; Network Clock Configuration &lt;BR /&gt;&amp;nbsp; --------------------------- &lt;BR /&gt;&amp;nbsp; Priority&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Clock Source&amp;nbsp;&amp;nbsp;&amp;nbsp; Clock State&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Clock Type &lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; 10&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Backplane&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; GOOD&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; PLL&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/P&gt;&lt;P&gt;&amp;nbsp; Current Primary Clock Source &lt;BR /&gt;&amp;nbsp; --------------------------- &lt;BR /&gt;&amp;nbsp; Priority&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Clock Source&amp;nbsp;&amp;nbsp;&amp;nbsp; Clock State&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Clock Type &lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; 10&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Backplane&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; GOOD&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; PLL&amp;nbsp; &lt;/P&gt;&lt;P&gt;------------------------------------------------------&lt;/P&gt;&lt;P&gt;#sh run | in network&lt;/P&gt;&lt;P&gt;network-clock-participate wic 0&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;thanks, &lt;/P&gt;</description>
      <pubDate>Mon, 04 Mar 2019 21:52:40 GMT</pubDate>
      <guid>https://community.cisco.com/t5/routing-and-sd-wan/pri-backplane-clock-source/m-p/1753962#M171528</guid>
      <dc:creator>Muralidharan.p</dc:creator>
      <dc:date>2019-03-04T21:52:40Z</dc:date>
    </item>
    <item>
      <title>Re: PRI backplane clock source</title>
      <link>https://community.cisco.com/t5/routing-and-sd-wan/pri-backplane-clock-source/m-p/1753963#M171529</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;PRI controllers need to derive the clock from the backplane so that the E1 is synced to the PVDMs. Unfortunately, in this case, both E1 lines cannot operate independently. Add this to the config &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;"network-clock-select 1 e1 0/0/0"&lt;/P&gt;&lt;P&gt;"network-clock-select 2 e1 0/0/1"&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;After this, do a "clear controller e1". This would cause both controllers to dervice their clocking from the backplane, which in turn will now derive clocking from the lines. Look at this for reference&lt;/P&gt;&lt;P&gt;&lt;A href="http://www.cisco.com/en/US/docs/ios/12_3t/voice/command/reference/vrht_n1_ps5207_TSD_Products_Command_Reference_Chapter.html#wp1017019"&gt;http://www.cisco.com/en/US/docs/ios/12_3t/voice/command/reference/vrht_n1_ps5207_TSD_Products_Command_Reference_Chapter.html#wp1017019&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If both lines are from the same provider, both will be cleared of the errors, otherwise, only the 1st would be. &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 10 Oct 2011 11:40:42 GMT</pubDate>
      <guid>https://community.cisco.com/t5/routing-and-sd-wan/pri-backplane-clock-source/m-p/1753963#M171529</guid>
      <dc:creator>Ronit Bhattacharjee</dc:creator>
      <dc:date>2011-10-10T11:40:42Z</dc:date>
    </item>
    <item>
      <title>Re: PRI backplane clock source</title>
      <link>https://community.cisco.com/t5/routing-and-sd-wan/pri-backplane-clock-source/m-p/1753964#M171530</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Great, thanks for the reply Ronit. Can you confirm me whether the provider also need to be configure the controller e1 0/0/0 as primary?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 10 Oct 2011 11:54:42 GMT</pubDate>
      <guid>https://community.cisco.com/t5/routing-and-sd-wan/pri-backplane-clock-source/m-p/1753964#M171530</guid>
      <dc:creator>Muralidharan.p</dc:creator>
      <dc:date>2011-10-10T11:54:42Z</dc:date>
    </item>
    <item>
      <title>Re: PRI backplane clock source</title>
      <link>https://community.cisco.com/t5/routing-and-sd-wan/pri-backplane-clock-source/m-p/1753965#M171531</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Murali,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The only thing the provider needs to do is make sure both lines have synchronized clocking.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 10 Oct 2011 11:58:33 GMT</pubDate>
      <guid>https://community.cisco.com/t5/routing-and-sd-wan/pri-backplane-clock-source/m-p/1753965#M171531</guid>
      <dc:creator>Ronit Bhattacharjee</dc:creator>
      <dc:date>2011-10-10T11:58:33Z</dc:date>
    </item>
    <item>
      <title>PRI backplane clock source</title>
      <link>https://community.cisco.com/t5/routing-and-sd-wan/pri-backplane-clock-source/m-p/1753966#M171532</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt; Thanks a lot Ronit, let me check with provider. &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 10 Oct 2011 12:01:34 GMT</pubDate>
      <guid>https://community.cisco.com/t5/routing-and-sd-wan/pri-backplane-clock-source/m-p/1753966#M171532</guid>
      <dc:creator>Muralidharan.p</dc:creator>
      <dc:date>2011-10-10T12:01:34Z</dc:date>
    </item>
    <item>
      <title>PRI backplane clock source</title>
      <link>https://community.cisco.com/t5/routing-and-sd-wan/pri-backplane-clock-source/m-p/1753967#M171533</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Ronit, one quick question, whether the command "network-clock-select 1 e1 0/0/0" will reset the PRIs? This is the besiness hrs for us.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 10 Oct 2011 12:04:56 GMT</pubDate>
      <guid>https://community.cisco.com/t5/routing-and-sd-wan/pri-backplane-clock-source/m-p/1753967#M171533</guid>
      <dc:creator>Muralidharan.p</dc:creator>
      <dc:date>2011-10-10T12:04:56Z</dc:date>
    </item>
    <item>
      <title>Re: PRI backplane clock source</title>
      <link>https://community.cisco.com/t5/routing-and-sd-wan/pri-backplane-clock-source/m-p/1753968#M171534</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Murali,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;It might. I am not sure. I would recommend that you try this after-hours or during a break/maintenance-window.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 10 Oct 2011 12:10:03 GMT</pubDate>
      <guid>https://community.cisco.com/t5/routing-and-sd-wan/pri-backplane-clock-source/m-p/1753968#M171534</guid>
      <dc:creator>Ronit Bhattacharjee</dc:creator>
      <dc:date>2011-10-10T12:10:03Z</dc:date>
    </item>
    <item>
      <title>PRI backplane clock source</title>
      <link>https://community.cisco.com/t5/routing-and-sd-wan/pri-backplane-clock-source/m-p/1753969#M171535</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt; Hi Ronit,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thaks a lot for the help, the issue has been resolved. FYI the controller was not reset while applying the config.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 11 Oct 2011 07:15:20 GMT</pubDate>
      <guid>https://community.cisco.com/t5/routing-and-sd-wan/pri-backplane-clock-source/m-p/1753969#M171535</guid>
      <dc:creator>Muralidharan.p</dc:creator>
      <dc:date>2011-10-11T07:15:20Z</dc:date>
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