<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: Strange issue when using dual ESP100 in combination with MIP100 in Routing</title>
    <link>https://community.cisco.com/t5/routing/strange-issue-when-using-dual-esp100-in-combination-with-mip100/m-p/4714886#M374325</link>
    <description>&lt;P&gt;Hi pieterh,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The strange thing is that they have another chassis with exactly the same config and they don't get any message so far.&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;</description>
    <pubDate>Wed, 02 Nov 2022 14:21:35 GMT</pubDate>
    <dc:creator>saul alonso ramos</dc:creator>
    <dc:date>2022-11-02T14:21:35Z</dc:date>
    <item>
      <title>Strange issue when using dual ESP100 in combination with MIP100</title>
      <link>https://community.cisco.com/t5/routing/strange-issue-when-using-dual-esp100-in-combination-with-mip100/m-p/4714807#M374317</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;Trying to help a customer I found an strange issue, if below configuration is present, all works fine:&lt;/P&gt;&lt;P&gt;Router#show platform&lt;BR /&gt;Chassis type: ASR1009-X&lt;/P&gt;&lt;P&gt;Slot Type State Insert time (ago)&lt;BR /&gt;--------- ------------------- --------------------- -----------------&lt;BR /&gt;1 ASR1000-MIP100 ok 00:15:02&lt;BR /&gt;2 ASR1000-MIP100 ok 00:26:33&lt;BR /&gt;R0 ASR1000-RP3 ok, active 00:39:11&lt;BR /&gt;R1 ASR1000-RP3 ok, standby 00:18:21&lt;BR /&gt;F0 ASR1000-ESP100 ok, active 00:39:11&lt;BR /&gt;P0 ASR1000X-AC-1100W ok 00:38:03&lt;BR /&gt;P1 ASR1000X-AC-1100W ok 00:38:00&lt;BR /&gt;P2 ASR1000X-AC-1100W ok 00:37:56&lt;BR /&gt;P3 ASR1000X-AC-1100W ok 00:37:51&lt;BR /&gt;P4 ASR1000X-AC-1100W ok 00:37:49&lt;BR /&gt;P5 ASR1000X-AC-1100W ok 00:37:46&lt;BR /&gt;P6 ASR1000X-FAN ok 00:37:32&lt;BR /&gt;P7 ASR1000X-FAN ok 00:37:31&lt;BR /&gt;P8 ASR1000X-FAN ok 00:37:33&lt;/P&gt;&lt;P&gt;Slot CPLD Version Firmware Version&lt;BR /&gt;--------- ------------------- ---------------------------------------&lt;BR /&gt;1 15072100 16.3(2r)&lt;BR /&gt;2 15072100 16.3(2r)&lt;BR /&gt;R0 17042115 17.3(1r)&lt;BR /&gt;R1 17042115 17.3(1r)&lt;BR /&gt;F0 12071700 17.3(1r)&lt;/P&gt;&lt;P&gt;Router#&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;But in the moment I insert the other ASR1000-ESP100 I start to get the below messages:&lt;/P&gt;&lt;P&gt;*Nov 2 12:35:08.062: %CMRP-6-FP_HA_STATUS: R0/0: cmand: F0 redundancy state is Active with ready Standby&lt;BR /&gt;*Nov 2 12:35:19.153: %SCOOBY-5-SERIAL_BRIDGE_BLOCK_EVENT: F1/0: cman_fp: Block qesi-chico_set1-CC2/11 of serial bridge 0 had I/O event 0xf800&lt;BR /&gt;*Nov 2 12:35:22.556: %SCOOBY-5-SERIAL_BRIDGE_BLOCK_EVENT: C2/0: cmcc: Block qesi-chico_set1-FP1/15 of serial bridge 0 had I/O event 0xd800&lt;BR /&gt;*Nov 2 12:35:34.155: %SCOOBY-5-SERIAL_BRIDGE_BLOCK_EVENT: F1/0: cman_fp: Block qesi-chico_set1-CC2/11 of serial bridge 0 had I/O event 0xd800&lt;BR /&gt;*Nov 2 12:35:37.689: %SCOOBY-5-SERIAL_BRIDGE_BLOCK_EVENT: C2/0: cmcc: Block qesi-chico_set1-FP1/15 of serial bridge 0 had I/O event 0x9800&lt;BR /&gt;*Nov 2 12:35:49.156: %SCOOBY-5-SERIAL_BRIDGE_BLOCK_EVENT: F1/0: cman_fp: Block qesi-chico_set1-CC2/11 of serial bridge 0 had I/O event 0xd000&lt;BR /&gt;*Nov 2 12:35:52.826: %SCOOBY-5-SERIAL_BRIDGE_BLOCK_EVENT: C2/0: cmcc: Block qesi-chico_set1-FP1/15 of serial bridge 0 had I/O event 0xd800&lt;BR /&gt;*Nov 2 12:36:04.157: %SCOOBY-5-SERIAL_BRIDGE_BLOCK_EVENT: F1/0: cman_fp: Block qesi-chico_set1-CC2/11 of serial bridge 0 had I/O event 0xd800&lt;BR /&gt;Router#&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;If only one ESP is present, doesn't matter the slot its plugged in, the message will not show.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Router#show ver&lt;BR /&gt;Cisco IOS XE Software, Version 17.06.04&lt;BR /&gt;Cisco IOS Software [Bengaluru], ASR1000 Software (X86_64_LINUX_IOSD-UNIVERSALK9-M), Version 17.6.4, RELEASE SOFTWARE (fc1)&lt;BR /&gt;Technical Support: &lt;A href="http://www.cisco.com/techsupport" target="_blank"&gt;http://www.cisco.com/techsupport&lt;/A&gt;&lt;BR /&gt;Copyright (c) 1986-2022 by Cisco Systems, Inc.&lt;BR /&gt;Compiled Sun 14-Aug-22 08:52 by mcpre&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Cisco IOS-XE software, Copyright (c) 2005-2022 by cisco Systems, Inc.&lt;BR /&gt;All rights reserved. Certain components of Cisco IOS-XE software are&lt;BR /&gt;licensed under the GNU General Public License ("GPL") Version 2.0. The&lt;BR /&gt;software code licensed under GPL Version 2.0 is free software that comes&lt;BR /&gt;with ABSOLUTELY NO WARRANTY. You can redistribute and/or modify such&lt;BR /&gt;GPL code under the terms of GPL Version 2.0. For more details, see the&lt;BR /&gt;documentation or "License Notice" file accompanying the IOS-XE software,&lt;BR /&gt;or the applicable URL provided on the flyer accompanying the IOS-XE&lt;BR /&gt;software.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;ROM: 17.3(1r)&lt;/P&gt;&lt;P&gt;Router uptime is 46 minutes&lt;BR /&gt;Uptime for this control processor is 49 minutes&lt;BR /&gt;System returned to ROM by Reload Command at 11:38:17 UTC Wed Nov 2 2022&lt;BR /&gt;System image file is "bootflash:asr1000rpx86-universalk9.17.06.04.SPA.bin"&lt;BR /&gt;Last reload reason: Reload Command&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;This product contains cryptographic features and is subject to United&lt;BR /&gt;States and local country laws governing import, export, transfer and&lt;BR /&gt;use. Delivery of Cisco cryptographic products does not imply&lt;BR /&gt;third-party authority to import, export, distribute or use encryption.&lt;BR /&gt;Importers, exporters, distributors and users are responsible for&lt;BR /&gt;compliance with U.S. and local country laws. By using this product you&lt;BR /&gt;agree to comply with applicable laws and regulations. If you are unable&lt;BR /&gt;to comply with U.S. and local laws, return this product immediately.&lt;/P&gt;&lt;P&gt;A summary of U.S. laws governing Cisco cryptographic products may be found at:&lt;BR /&gt;&lt;A href="http://www.cisco.com/wwl/export/crypto/tool/stqrg.html" target="_blank"&gt;http://www.cisco.com/wwl/export/crypto/tool/stqrg.html&lt;/A&gt;&lt;/P&gt;&lt;P&gt;If you require further assistance please contact us by sending email to&lt;BR /&gt;export@cisco.com.&lt;/P&gt;&lt;P&gt;License Type: Smart License is permanent&lt;BR /&gt;License Level: adventerprise&lt;BR /&gt;Next reload license Level: adventerprise&lt;/P&gt;&lt;P&gt;Smart Licensing Status: Registration Not Applicable/Not Applicable&lt;/P&gt;&lt;P&gt;cisco ASR1009-X (RP3) processor (revision RP3) with 15006187K/24590K bytes of memory.&lt;BR /&gt;Processor board ID FXS2204Q3Z0&lt;BR /&gt;Router operating mode: Autonomous&lt;BR /&gt;32768K bytes of non-volatile configuration memory.&lt;BR /&gt;33554432K bytes of physical memory.&lt;BR /&gt;7116799K bytes of eUSB flash at bootflash:.&lt;BR /&gt;97620247K bytes of SATA hard disk at harddisk:.&lt;/P&gt;&lt;P&gt;Configuration register is 0x2102&lt;/P&gt;&lt;P&gt;Router#&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Could someone shred some light on this issue?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks!&lt;/P&gt;</description>
      <pubDate>Wed, 02 Nov 2022 11:38:45 GMT</pubDate>
      <guid>https://community.cisco.com/t5/routing/strange-issue-when-using-dual-esp100-in-combination-with-mip100/m-p/4714807#M374317</guid>
      <dc:creator>saul alonso ramos</dc:creator>
      <dc:date>2022-11-02T11:38:45Z</dc:date>
    </item>
    <item>
      <title>Re: Strange issue when using dual ESP100 in combination with MIP100</title>
      <link>https://community.cisco.com/t5/routing/strange-issue-when-using-dual-esp100-in-combination-with-mip100/m-p/4714844#M374322</link>
      <description>&lt;P&gt;this document is for IOS-XE version 16, but states the log is cosmetic&lt;BR /&gt;&lt;A href="https://www.cisco.com/c/en/us/td/docs/ios-xml/ios/16_xe/smg/xe-16-10/b-sem-16-10-1/b-sem-16-10-1_chapter_0110.html" target="_blank"&gt;System Error Messages Guide For Access and Edge Routers, Cisco IOS XE Gibraltar 16.10.1 - SBC_MPS through TMQ [Cisco IOS XE 16] - Cisco&lt;/A&gt;&lt;/P&gt;
&lt;TABLE id="r-sem-16-10-1-SBC_MPS-to-SENSORMGR__sec-SCOOBY-tab1" class="table frame-topbot" border="1" width="100%"&gt;&lt;CAPTION&gt;&amp;nbsp;&lt;/CAPTION&gt;&lt;COLGROUP&gt;&lt;COL /&gt;&lt;COL /&gt;&lt;/COLGROUP&gt;
&lt;THEAD class="thead"&gt;
&lt;TR class="row"&gt;
&lt;TH id="r-sem-16-10-1-SBC_MPS-to-SENSORMGR__sec-SCOOBY-tab1__entry__1" class="entry colsep-0 rowsep-0" colspan="2"&gt;%SCOOBY-5-SERIAL_BRIDGE_BLOCK_EVENT : Block [chars]/[dec] of serial bridge [dec] had I/O event [hex]&lt;/TH&gt;
&lt;/TR&gt;
&lt;/THEAD&gt;
&lt;TBODY class="tbody"&gt;
&lt;TR class="row"&gt;
&lt;TD class="entry colsep-0 rowsep-0"&gt;&lt;STRONG class="ph b"&gt;Explanation&lt;/STRONG&gt;&lt;/TD&gt;
&lt;TD class="entry colsep-0 rowsep-0"&gt;A serial bridge I/O event has occurred. This event is not serious but is logged for diagnostic purposes.&lt;/TD&gt;
&lt;/TR&gt;
&lt;TR class="row"&gt;
&lt;TD class="entry colsep-0 rowsep-0"&gt;&lt;STRONG class="ph b"&gt;Recommended Action&lt;/STRONG&gt;&lt;/TD&gt;
&lt;TD class="entry colsep-0 rowsep-0"&gt;No user action is required.&lt;/TD&gt;
&lt;/TR&gt;
&lt;/TBODY&gt;
&lt;/TABLE&gt;</description>
      <pubDate>Wed, 02 Nov 2022 13:06:35 GMT</pubDate>
      <guid>https://community.cisco.com/t5/routing/strange-issue-when-using-dual-esp100-in-combination-with-mip100/m-p/4714844#M374322</guid>
      <dc:creator>pieterh</dc:creator>
      <dc:date>2022-11-02T13:06:35Z</dc:date>
    </item>
    <item>
      <title>Re: Strange issue when using dual ESP100 in combination with MIP100</title>
      <link>https://community.cisco.com/t5/routing/strange-issue-when-using-dual-esp100-in-combination-with-mip100/m-p/4714886#M374325</link>
      <description>&lt;P&gt;Hi pieterh,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The strange thing is that they have another chassis with exactly the same config and they don't get any message so far.&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;</description>
      <pubDate>Wed, 02 Nov 2022 14:21:35 GMT</pubDate>
      <guid>https://community.cisco.com/t5/routing/strange-issue-when-using-dual-esp100-in-combination-with-mip100/m-p/4714886#M374325</guid>
      <dc:creator>saul alonso ramos</dc:creator>
      <dc:date>2022-11-02T14:21:35Z</dc:date>
    </item>
    <item>
      <title>Re: Strange issue when using dual ESP100 in combination with MIP100</title>
      <link>https://community.cisco.com/t5/routing/strange-issue-when-using-dual-esp100-in-combination-with-mip100/m-p/4716949#M374472</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;See attached a bit more info, take into account that these two chassis/card combination are exactly the same (and running the same IOS-XR) so, if was cosmetic, I would expect to have the same errors in both chassis:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;RP/0/RSP1/CPU0:W4A#show controller np ports all location 0/0/CPU0&lt;BR /&gt;Fri Nov 4 16:24:44.096 CET&lt;/P&gt;&lt;P&gt;Node: 0/0/CPU0:&lt;BR /&gt;----------------------------------------------------------------&lt;/P&gt;&lt;P&gt;CPX NP Bridge Fia Ports&lt;BR /&gt;--- -- ------ --- ----------------------------------------------&lt;BR /&gt;0 0 0 0 HundredGigE0/0/0/1&lt;BR /&gt;0 1 0 1 HundredGigE0/0/0/1&lt;BR /&gt;1 2 1 2 HundredGigE0/0/0/0&lt;BR /&gt;1 3 1 3 HundredGigE0/0/0/0&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Then with the command below I identified that in bridge 1 (the one that controls the offending port) there are various errors:&lt;/P&gt;&lt;P&gt;RP/0/RSP1/CPU0:W4A#show controllers fabric fia bridge stats location 0/0/CPU0&lt;BR /&gt;Fri Nov 4 16:46:50.210 CET&lt;/P&gt;&lt;P&gt;********** FIA-0 **********&lt;BR /&gt;Category: bridge_in-0&lt;BR /&gt;To FIA0 L-0 1975908298&lt;BR /&gt;To FIA0 L-1 22657962790&lt;BR /&gt;To FIA1 L-0 25593342316&lt;BR /&gt;To FIA1 L-1 2394174402&lt;BR /&gt;Frm NPU ilk 52621387810&lt;BR /&gt;Frm NPU Pkt 52621387812&lt;BR /&gt;MC Ch0 Pkt drp 0&lt;BR /&gt;MC Ch1 Pkt drp 0&lt;BR /&gt;MC Ch2 Pkt drp 0&lt;BR /&gt;MC Ch3 Pkt drp 0&lt;BR /&gt;FIA00 Tx Err 0&lt;BR /&gt;FIA01 Tx Err 0&lt;BR /&gt;FIA10 Tx Err 0&lt;BR /&gt;FIA11 Tx Err 0&lt;BR /&gt;NP Err1 Cnt 0&lt;BR /&gt;NP Err2 Cnt 0&lt;BR /&gt;NP Err3 Cnt 0&lt;BR /&gt;NP Err4 Cnt 0&lt;BR /&gt;NP WrdSync1 0&lt;BR /&gt;NP WrdSync2 0&lt;BR /&gt;NP WrdSync3 0&lt;BR /&gt;NP WrdSync4 0&lt;BR /&gt;NP WrdSync5 0&lt;BR /&gt;NP WrdSync6 0&lt;BR /&gt;NP MFrm Err1 0&lt;BR /&gt;NP MFrm Err2 0&lt;BR /&gt;NP MFrm Err3 0&lt;BR /&gt;NP MFrm Err4 0&lt;BR /&gt;NP MFrm Err5 0&lt;BR /&gt;NP MFrm Err6 0&lt;BR /&gt;NP BType Err1 0&lt;BR /&gt;NP BType Err2 0&lt;BR /&gt;NP BType Err3 0&lt;BR /&gt;NP BType Err4 0&lt;BR /&gt;NP BType Err5 0&lt;BR /&gt;NP BType Err6 0&lt;BR /&gt;NP MFrmSync1 0&lt;BR /&gt;NP MFrmSync2 0&lt;BR /&gt;NP MFrmSync3 0&lt;BR /&gt;NP MFrmSync4 0&lt;BR /&gt;NP MFrmSync5 0&lt;BR /&gt;NP MFrmSync6 0&lt;BR /&gt;NP MFrmLn Err1 0&lt;BR /&gt;NP MFrmLn Err2 0&lt;BR /&gt;NP MFrmLn Err3 0&lt;BR /&gt;NP MFrmLn Err4 0&lt;BR /&gt;NP MFrmLn Err5 0&lt;BR /&gt;NP MFrmLn Err6 0&lt;/P&gt;&lt;P&gt;********** FIA-0 **********&lt;BR /&gt;Category: bridge_eg-0&lt;BR /&gt;FIA0 L-0 ilk 18551480573&lt;BR /&gt;FIA0 L-1 ilk 18151690715&lt;BR /&gt;FIA1 L-0 ilk 704245493002&lt;BR /&gt;FIA1 L-1 ilk 18668799906&lt;BR /&gt;FIA0 L-0 Pkt 18551480576&lt;BR /&gt;FIA0 L-1 Pkt 18151690718&lt;BR /&gt;FIA1 L-0 Pkt 704245493007&lt;BR /&gt;FIA1 L-1 Pkt 18668799908&lt;BR /&gt;To NPU 759617464248&lt;BR /&gt;UC LO Pkt ctr 758964674469&lt;BR /&gt;UC HI Pkt ctr 16613759&lt;BR /&gt;MC LO Pkt ctr 1003120&lt;BR /&gt;MC HI Pkt ctr 635172902&lt;BR /&gt;UC LO Pkt drp 0&lt;BR /&gt;UC HI Pkt drp 0&lt;BR /&gt;MC LO Pkt drp 0&lt;BR /&gt;MC HI Pkt drp 0&lt;BR /&gt;FIA00 Pkt drp 0&lt;BR /&gt;FIA01 Pkt drp 0&lt;BR /&gt;FIA10 Pkt drp 0&lt;BR /&gt;FIA11 Pkt drp 0&lt;BR /&gt;NPU Err Cnt 0&lt;BR /&gt;FIA00 Rx Err 0&lt;BR /&gt;FIA00 ilk Err 0&lt;BR /&gt;FIA00 crc Err 0&lt;BR /&gt;FIA00 seq Err 0&lt;BR /&gt;FIA01 Rx Err 0&lt;BR /&gt;FIA01 ilk Err 0&lt;BR /&gt;FIA01 crc Err 0&lt;BR /&gt;FIA01 seq Err 0&lt;BR /&gt;FIA10 Rx Err 0&lt;BR /&gt;FIA10 ilk Err 0&lt;BR /&gt;FIA10 crc Err 0&lt;BR /&gt;FIA10 seq Err 0&lt;BR /&gt;FIA11 Rx Err 0&lt;BR /&gt;FIA11 ilk Err 0&lt;BR /&gt;FIA11 crc Err 0&lt;BR /&gt;FIA11 seq Err 0&lt;BR /&gt;FIA00 crc1 Err 0&lt;BR /&gt;FIA00 crc2 Err 0&lt;BR /&gt;FIA01 crc1 Err 0&lt;BR /&gt;FIA01 crc2 Err 0&lt;BR /&gt;FIA10 crc1 Err 0&lt;BR /&gt;FIA10 crc2 Err 0&lt;BR /&gt;FIA11 crc1 Err 0&lt;BR /&gt;FIA11 crc2 Err 0&lt;/P&gt;&lt;P&gt;********** FIA-1 **********&lt;BR /&gt;Category: bridge_in-1&lt;BR /&gt;To FIA0 L-0 1897378903970&lt;BR /&gt;To FIA0 L-1 716307026477&lt;BR /&gt;To FIA1 L-0 14725384592&lt;BR /&gt;To FIA1 L-1 796301087214&lt;BR /&gt;Frm NPU ilk 3424712402254&lt;BR /&gt;Frm NPU Pkt 3424712402257&lt;BR /&gt;MC Ch0 Pkt drp 0&lt;BR /&gt;MC Ch1 Pkt drp 0&lt;BR /&gt;MC Ch2 Pkt drp 0&lt;BR /&gt;MC Ch3 Pkt drp 0&lt;BR /&gt;FIA00 Tx Err 0&lt;BR /&gt;FIA01 Tx Err 0&lt;BR /&gt;FIA10 Tx Err 0&lt;BR /&gt;FIA11 Tx Err 0&lt;BR /&gt;NP Err1 Cnt 0&lt;BR /&gt;NP Err2 Cnt 0&lt;BR /&gt;NP Err3 Cnt 0&lt;BR /&gt;NP Err4 Cnt 0&lt;BR /&gt;NP WrdSync1 0&lt;BR /&gt;NP WrdSync2 0&lt;BR /&gt;NP WrdSync3 0&lt;BR /&gt;NP WrdSync4 0&lt;BR /&gt;NP WrdSync5 0&lt;BR /&gt;NP WrdSync6 0&lt;BR /&gt;NP MFrm Err1 0&lt;BR /&gt;NP MFrm Err2 0&lt;BR /&gt;NP MFrm Err3 0&lt;BR /&gt;NP MFrm Err4 0&lt;BR /&gt;NP MFrm Err5 0&lt;BR /&gt;NP MFrm Err6 0&lt;BR /&gt;NP BType Err1 0&lt;BR /&gt;NP BType Err2 0&lt;BR /&gt;NP BType Err3 0&lt;BR /&gt;NP BType Err4 0&lt;BR /&gt;NP BType Err5 0&lt;BR /&gt;NP BType Err6 0&lt;BR /&gt;NP MFrmSync1 0&lt;BR /&gt;NP MFrmSync2 0&lt;BR /&gt;NP MFrmSync3 0&lt;BR /&gt;NP MFrmSync4 0&lt;BR /&gt;NP MFrmSync5 0&lt;BR /&gt;NP MFrmSync6 0&lt;BR /&gt;NP MFrmLn Err1 0&lt;BR /&gt;NP MFrmLn Err2 0&lt;BR /&gt;NP MFrmLn Err3 0&lt;BR /&gt;NP MFrmLn Err4 0&lt;BR /&gt;NP MFrmLn Err5 0&lt;BR /&gt;NP MFrmLn Err6 0&lt;/P&gt;&lt;P&gt;********** FIA-1 **********&lt;BR /&gt;Category: bridge_eg-1&lt;BR /&gt;FIA0 L-0 ilk 1745875069&lt;BR /&gt;FIA0 L-1 ilk 1430103512&lt;BR /&gt;FIA1 L-0 ilk 38157078790&lt;BR /&gt;FIA1 L-1 ilk 1424658053&lt;BR /&gt;FIA0 L-0 Pkt 1745875070&lt;BR /&gt;FIA0 L-1 Pkt 1430103513&lt;BR /&gt;FIA1 L-0 Pkt 38157078795&lt;BR /&gt;FIA1 L-1 Pkt 1424615986&lt;BR /&gt;To NPU 42757673372&lt;BR /&gt;UC LO Pkt ctr 42375120096&lt;BR /&gt;UC HI Pkt ctr 982848&lt;BR /&gt;MC LO Pkt ctr 91752&lt;BR /&gt;MC HI Pkt ctr 381478679&lt;BR /&gt;UC LO Pkt drp 0&lt;BR /&gt;UC HI Pkt drp 0&lt;BR /&gt;MC LO Pkt drp 0&lt;BR /&gt;MC HI Pkt drp 0&lt;BR /&gt;FIA00 Pkt drp 0&lt;BR /&gt;FIA01 Pkt drp 0&lt;BR /&gt;FIA10 Pkt drp 0&lt;BR /&gt;FIA11 Pkt drp 0&lt;BR /&gt;NPU Err Cnt 0&lt;BR /&gt;FIA00 Rx Err 0&lt;BR /&gt;FIA00 ilk Err 0&lt;BR /&gt;FIA00 crc Err 0&lt;BR /&gt;FIA00 seq Err 0&lt;BR /&gt;FIA01 Rx Err 0&lt;BR /&gt;FIA01 ilk Err 0&lt;BR /&gt;FIA01 crc Err 0&lt;BR /&gt;FIA01 seq Err 0&lt;BR /&gt;FIA10 Rx Err 0&lt;BR /&gt;FIA10 ilk Err 0&lt;BR /&gt;FIA10 crc Err 0&lt;BR /&gt;FIA10 seq Err 0&lt;BR /&gt;FIA11 Rx Err 52212&lt;BR /&gt;FIA11 ilk Err 365441&lt;BR /&gt;FIA11 crc Err 3786383512&lt;BR /&gt;FIA11 seq Err 1&lt;BR /&gt;FIA00 crc1 Err 0&lt;BR /&gt;FIA00 crc2 Err 0&lt;BR /&gt;FIA01 crc1 Err 0&lt;BR /&gt;FIA01 crc2 Err 0&lt;BR /&gt;FIA10 crc1 Err 0&lt;BR /&gt;FIA10 crc2 Err 0&lt;BR /&gt;FIA11 crc1 Err 3783754038&lt;BR /&gt;FIA11 crc2 Err 0&lt;/P&gt;&lt;P&gt;RP/0/RSP1/CPU0:W4A#show controller fabric fia drop in location 0/0/CPU0&lt;BR /&gt;Fri Nov 4 17:00:32.660 CET&lt;/P&gt;&lt;P&gt;********** FIA-0 **********&lt;BR /&gt;Category: in_drop-0&lt;BR /&gt;From Spaui Drop-0 0&lt;BR /&gt;accpt tbl-0 0&lt;BR /&gt;ctl len-0 0&lt;BR /&gt;short pkt-0 0&lt;BR /&gt;max pkt len-0 0&lt;BR /&gt;min pkt len-0 0&lt;BR /&gt;From Spaui Drop-1 0&lt;BR /&gt;accpt tbl-1 0&lt;BR /&gt;ctl len-1 0&lt;BR /&gt;short pkt-1 0&lt;BR /&gt;max pkt len-1 0&lt;BR /&gt;min pkt len-1 0&lt;BR /&gt;Tail drp 0&lt;BR /&gt;Vqi drp 0&lt;BR /&gt;Header parsing drp 0&lt;BR /&gt;pw to ni drp 0&lt;BR /&gt;ni from pw drp 0&lt;BR /&gt;sp0 crc err 0&lt;BR /&gt;sp0 bad align 0&lt;BR /&gt;sp0 bad code 0&lt;BR /&gt;sp0 align fail 3&lt;BR /&gt;sp0 prot err 0&lt;BR /&gt;sp1 crc err 16&lt;BR /&gt;sp1 bad align 0&lt;BR /&gt;sp1 bad code 16&lt;BR /&gt;sp1 align fail 3&lt;BR /&gt;sp1 prot err 3&lt;/P&gt;&lt;P&gt;********** FIA-1 **********&lt;BR /&gt;Category: in_drop-1&lt;BR /&gt;From Spaui Drop-0 0&lt;BR /&gt;accpt tbl-0 0&lt;BR /&gt;ctl len-0 0&lt;BR /&gt;short pkt-0 0&lt;BR /&gt;max pkt len-0 0&lt;BR /&gt;min pkt len-0 0&lt;BR /&gt;From Spaui Drop-1 0&lt;BR /&gt;accpt tbl-1 0&lt;BR /&gt;ctl len-1 0&lt;BR /&gt;short pkt-1 0&lt;BR /&gt;max pkt len-1 0&lt;BR /&gt;min pkt len-1 0&lt;BR /&gt;Tail drp 0&lt;BR /&gt;Vqi drp 0&lt;BR /&gt;Header parsing drp 0&lt;BR /&gt;pw to ni drp 0&lt;BR /&gt;ni from pw drp 0&lt;BR /&gt;sp0 crc err 1&lt;BR /&gt;sp0 bad align 0&lt;BR /&gt;sp0 bad code 0&lt;BR /&gt;sp0 align fail 3&lt;BR /&gt;sp0 prot err 0&lt;BR /&gt;sp1 crc err 0&lt;BR /&gt;sp1 bad align 0&lt;BR /&gt;sp1 bad code 0&lt;BR /&gt;sp1 align fail 3&lt;BR /&gt;sp1 prot err 0&lt;/P&gt;&lt;P&gt;********** FIA-2 **********&lt;BR /&gt;Category: in_drop-2&lt;BR /&gt;From Spaui Drop-0 0&lt;BR /&gt;accpt tbl-0 0&lt;BR /&gt;ctl len-0 0&lt;BR /&gt;short pkt-0 0&lt;BR /&gt;max pkt len-0 0&lt;BR /&gt;min pkt len-0 0&lt;BR /&gt;From Spaui Drop-1 0&lt;BR /&gt;accpt tbl-1 0&lt;BR /&gt;ctl len-1 0&lt;BR /&gt;short pkt-1 0&lt;BR /&gt;max pkt len-1 0&lt;BR /&gt;min pkt len-1 0&lt;BR /&gt;Tail drp 103685&lt;BR /&gt;Vqi drp 0&lt;BR /&gt;Header parsing drp 0&lt;BR /&gt;pw to ni drp 0&lt;BR /&gt;ni from pw drp 0&lt;BR /&gt;sp0 crc err 0&lt;BR /&gt;sp0 bad align 0&lt;BR /&gt;sp0 bad code 0&lt;BR /&gt;sp0 align fail 3&lt;BR /&gt;sp0 prot err 0&lt;BR /&gt;sp1 crc err 0&lt;BR /&gt;sp1 bad align 0&lt;BR /&gt;sp1 bad code 0&lt;BR /&gt;sp1 align fail 3&lt;BR /&gt;sp1 prot err 0&lt;/P&gt;&lt;P&gt;********** FIA-3 **********&lt;BR /&gt;Category: in_drop-3&lt;BR /&gt;From Spaui Drop-0 0&lt;BR /&gt;accpt tbl-0 0&lt;BR /&gt;ctl len-0 0&lt;BR /&gt;short pkt-0 0&lt;BR /&gt;max pkt len-0 0&lt;BR /&gt;min pkt len-0 0&lt;BR /&gt;From Spaui Drop-1 0&lt;BR /&gt;accpt tbl-1 0&lt;BR /&gt;ctl len-1 0&lt;BR /&gt;short pkt-1 0&lt;BR /&gt;max pkt len-1 0&lt;BR /&gt;min pkt len-1 0&lt;BR /&gt;Tail drp 0&lt;BR /&gt;Vqi drp 0&lt;BR /&gt;Header parsing drp 0&lt;BR /&gt;pw to ni drp 0&lt;BR /&gt;ni from pw drp 0&lt;BR /&gt;sp0 crc err 0&lt;BR /&gt;sp0 bad align 0&lt;BR /&gt;sp0 bad code 0&lt;BR /&gt;sp0 align fail 3&lt;BR /&gt;sp0 prot err 0&lt;BR /&gt;sp1 crc err 7&lt;BR /&gt;sp1 bad align 0&lt;BR /&gt;sp1 bad code 4&lt;BR /&gt;sp1 align fail 3&lt;BR /&gt;sp1 prot err 0&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;RP/0/RSP1/CPU0:W4A#show controller fabric fia q-depth location 0/0/CPU0&lt;BR /&gt;Fri Nov 4 17:01:19.200 CET&lt;/P&gt;&lt;P&gt;********** FIA-0 **********&lt;BR /&gt;Category: q_stats_a-0&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;********** FIA-0 **********&lt;BR /&gt;Category: q_stats_b-0&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;********** FIA-1 **********&lt;BR /&gt;Category: q_stats_a-1&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;********** FIA-1 **********&lt;BR /&gt;Category: q_stats_b-1&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;********** FIA-2 **********&lt;BR /&gt;Category: q_stats_a-2&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;********** FIA-2 **********&lt;BR /&gt;Category: q_stats_b-2&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;********** FIA-3 **********&lt;BR /&gt;Category: q_stats_a-3&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;BR /&gt;312 0 2 1450 LC2_0_0&lt;/P&gt;&lt;P&gt;********** FIA-3 **********&lt;BR /&gt;Category: q_stats_b-3&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Finally I paste the output of the same 4 commands from the machine that has no problems:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;RP/0/RSP0/CPU0:NS3#show controller np ports all location 0/0/CPU0&lt;BR /&gt;Fri Nov 4 17:37:30.510 CET&lt;/P&gt;&lt;P&gt;Node: 0/0/CPU0:&lt;BR /&gt;----------------------------------------------------------------&lt;/P&gt;&lt;P&gt;CPX NP Bridge Fia Ports&lt;BR /&gt;--- -- ------ --- ----------------------------------------------&lt;BR /&gt;0 0 0 0 HundredGigE0/0/0/1&lt;BR /&gt;0 1 0 1 HundredGigE0/0/0/1&lt;BR /&gt;1 2 1 2 HundredGigE0/0/0/0&lt;BR /&gt;1 3 1 3 HundredGigE0/0/0/0&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;RP/0/RSP0/CPU0:NS3#show controllers fabric fia bridge stats location 0/0/CPU0&lt;BR /&gt;Fri Nov 4 17:37:59.049 CET&lt;/P&gt;&lt;P&gt;********** FIA-0 **********&lt;BR /&gt;Category: bridge_in-0&lt;BR /&gt;To FIA0 L-0 27477332927&lt;BR /&gt;To FIA0 L-1 27847393105&lt;BR /&gt;To FIA1 L-0 27774090133&lt;BR /&gt;To FIA1 L-1 28387156842&lt;BR /&gt;Frm NPU ilk 111485973012&lt;BR /&gt;Frm NPU Pkt 111485973014&lt;BR /&gt;MC Ch0 Pkt drp 0&lt;BR /&gt;MC Ch1 Pkt drp 0&lt;BR /&gt;MC Ch2 Pkt drp 0&lt;BR /&gt;MC Ch3 Pkt drp 0&lt;BR /&gt;FIA00 Tx Err 0&lt;BR /&gt;FIA01 Tx Err 0&lt;BR /&gt;FIA10 Tx Err 0&lt;BR /&gt;FIA11 Tx Err 0&lt;BR /&gt;NP Err1 Cnt 0&lt;BR /&gt;NP Err2 Cnt 0&lt;BR /&gt;NP Err3 Cnt 0&lt;BR /&gt;NP Err4 Cnt 0&lt;BR /&gt;NP WrdSync1 0&lt;BR /&gt;NP WrdSync2 0&lt;BR /&gt;NP WrdSync3 0&lt;BR /&gt;NP WrdSync4 0&lt;BR /&gt;NP WrdSync5 0&lt;BR /&gt;NP WrdSync6 0&lt;BR /&gt;NP MFrm Err1 0&lt;BR /&gt;NP MFrm Err2 0&lt;BR /&gt;NP MFrm Err3 0&lt;BR /&gt;NP MFrm Err4 0&lt;BR /&gt;NP MFrm Err5 0&lt;BR /&gt;NP MFrm Err6 0&lt;BR /&gt;NP BType Err1 0&lt;BR /&gt;NP BType Err2 0&lt;BR /&gt;NP BType Err3 0&lt;BR /&gt;NP BType Err4 0&lt;BR /&gt;NP BType Err5 0&lt;BR /&gt;NP BType Err6 0&lt;BR /&gt;NP MFrmSync1 0&lt;BR /&gt;NP MFrmSync2 0&lt;BR /&gt;NP MFrmSync3 0&lt;BR /&gt;NP MFrmSync4 0&lt;BR /&gt;NP MFrmSync5 0&lt;BR /&gt;NP MFrmSync6 0&lt;BR /&gt;NP MFrmLn Err1 0&lt;BR /&gt;NP MFrmLn Err2 0&lt;BR /&gt;NP MFrmLn Err3 0&lt;BR /&gt;NP MFrmLn Err4 0&lt;BR /&gt;NP MFrmLn Err5 0&lt;BR /&gt;NP MFrmLn Err6 0&lt;/P&gt;&lt;P&gt;********** FIA-0 **********&lt;BR /&gt;Category: bridge_eg-0&lt;BR /&gt;FIA0 L-0 ilk 57343383331&lt;BR /&gt;FIA0 L-1 ilk 56875518953&lt;BR /&gt;FIA1 L-0 ilk 57318428927&lt;BR /&gt;FIA1 L-1 ilk 57342623474&lt;BR /&gt;FIA0 L-0 Pkt 57343383334&lt;BR /&gt;FIA0 L-1 Pkt 56875518958&lt;BR /&gt;FIA1 L-0 Pkt 57318428932&lt;BR /&gt;FIA1 L-1 Pkt 57342623478&lt;BR /&gt;To NPU 228879954725&lt;BR /&gt;UC LO Pkt ctr 228152056244&lt;BR /&gt;UC HI Pkt ctr 79434304&lt;BR /&gt;MC LO Pkt ctr 240256&lt;BR /&gt;MC HI Pkt ctr 648223921&lt;BR /&gt;UC LO Pkt drp 0&lt;BR /&gt;UC HI Pkt drp 0&lt;BR /&gt;MC LO Pkt drp 0&lt;BR /&gt;MC HI Pkt drp 0&lt;BR /&gt;FIA00 Pkt drp 0&lt;BR /&gt;FIA01 Pkt drp 0&lt;BR /&gt;FIA10 Pkt drp 0&lt;BR /&gt;FIA11 Pkt drp 0&lt;BR /&gt;NPU Err Cnt 0&lt;BR /&gt;FIA00 Rx Err 0&lt;BR /&gt;FIA00 ilk Err 0&lt;BR /&gt;FIA00 crc Err 0&lt;BR /&gt;FIA00 seq Err 0&lt;BR /&gt;FIA01 Rx Err 0&lt;BR /&gt;FIA01 ilk Err 0&lt;BR /&gt;FIA01 crc Err 0&lt;BR /&gt;FIA01 seq Err 0&lt;BR /&gt;FIA10 Rx Err 0&lt;BR /&gt;FIA10 ilk Err 0&lt;BR /&gt;FIA10 crc Err 0&lt;BR /&gt;FIA10 seq Err 0&lt;BR /&gt;FIA11 Rx Err 0&lt;BR /&gt;FIA11 ilk Err 0&lt;BR /&gt;FIA11 crc Err 0&lt;BR /&gt;FIA11 seq Err 0&lt;BR /&gt;FIA00 crc1 Err 0&lt;BR /&gt;FIA00 crc2 Err 0&lt;BR /&gt;FIA01 crc1 Err 0&lt;BR /&gt;FIA01 crc2 Err 0&lt;BR /&gt;FIA10 crc1 Err 0&lt;BR /&gt;FIA10 crc2 Err 0&lt;BR /&gt;FIA11 crc1 Err 0&lt;BR /&gt;FIA11 crc2 Err 0&lt;/P&gt;&lt;P&gt;********** FIA-1 **********&lt;BR /&gt;Category: bridge_in-1&lt;BR /&gt;To FIA0 L-0 413523092710&lt;BR /&gt;To FIA0 L-1 408254651520&lt;BR /&gt;To FIA1 L-0 407426294052&lt;BR /&gt;To FIA1 L-1 1607159674927&lt;BR /&gt;Frm NPU ilk 2836363713215&lt;BR /&gt;Frm NPU Pkt 2836363713219&lt;BR /&gt;MC Ch0 Pkt drp 0&lt;BR /&gt;MC Ch1 Pkt drp 0&lt;BR /&gt;MC Ch2 Pkt drp 0&lt;BR /&gt;MC Ch3 Pkt drp 0&lt;BR /&gt;FIA00 Tx Err 0&lt;BR /&gt;FIA01 Tx Err 0&lt;BR /&gt;FIA10 Tx Err 0&lt;BR /&gt;FIA11 Tx Err 0&lt;BR /&gt;NP Err1 Cnt 0&lt;BR /&gt;NP Err2 Cnt 0&lt;BR /&gt;NP Err3 Cnt 0&lt;BR /&gt;NP Err4 Cnt 0&lt;BR /&gt;NP WrdSync1 0&lt;BR /&gt;NP WrdSync2 0&lt;BR /&gt;NP WrdSync3 0&lt;BR /&gt;NP WrdSync4 0&lt;BR /&gt;NP WrdSync5 0&lt;BR /&gt;NP WrdSync6 0&lt;BR /&gt;NP MFrm Err1 0&lt;BR /&gt;NP MFrm Err2 0&lt;BR /&gt;NP MFrm Err3 0&lt;BR /&gt;NP MFrm Err4 0&lt;BR /&gt;NP MFrm Err5 0&lt;BR /&gt;NP MFrm Err6 0&lt;BR /&gt;NP BType Err1 0&lt;BR /&gt;NP BType Err2 0&lt;BR /&gt;NP BType Err3 0&lt;BR /&gt;NP BType Err4 0&lt;BR /&gt;NP BType Err5 0&lt;BR /&gt;NP BType Err6 0&lt;BR /&gt;NP MFrmSync1 0&lt;BR /&gt;NP MFrmSync2 0&lt;BR /&gt;NP MFrmSync3 0&lt;BR /&gt;NP MFrmSync4 0&lt;BR /&gt;NP MFrmSync5 0&lt;BR /&gt;NP MFrmSync6 0&lt;BR /&gt;NP MFrmLn Err1 0&lt;BR /&gt;NP MFrmLn Err2 0&lt;BR /&gt;NP MFrmLn Err3 0&lt;BR /&gt;NP MFrmLn Err4 0&lt;BR /&gt;NP MFrmLn Err5 0&lt;BR /&gt;NP MFrmLn Err6 0&lt;/P&gt;&lt;P&gt;********** FIA-1 **********&lt;BR /&gt;Category: bridge_eg-1&lt;BR /&gt;FIA0 L-0 ilk 3400484549787&lt;BR /&gt;FIA0 L-1 ilk 105233491135&lt;BR /&gt;FIA1 L-0 ilk 102479840910&lt;BR /&gt;FIA1 L-1 ilk 101977545140&lt;BR /&gt;FIA0 L-0 Pkt 3400484549787&lt;BR /&gt;FIA0 L-1 Pkt 105233491136&lt;BR /&gt;FIA1 L-0 Pkt 102479840917&lt;BR /&gt;FIA1 L-1 Pkt 101977545143&lt;BR /&gt;To NPU 3710175426990&lt;BR /&gt;UC LO Pkt ctr 3709853180349&lt;BR /&gt;UC HI Pkt ctr 918672&lt;BR /&gt;MC LO Pkt ctr 95888&lt;BR /&gt;MC HI Pkt ctr 321232082&lt;BR /&gt;UC LO Pkt drp 0&lt;BR /&gt;UC HI Pkt drp 0&lt;BR /&gt;MC LO Pkt drp 0&lt;BR /&gt;MC HI Pkt drp 0&lt;BR /&gt;FIA00 Pkt drp 0&lt;BR /&gt;FIA01 Pkt drp 0&lt;BR /&gt;FIA10 Pkt drp 0&lt;BR /&gt;FIA11 Pkt drp 0&lt;BR /&gt;NPU Err Cnt 0&lt;BR /&gt;FIA00 Rx Err 0&lt;BR /&gt;FIA00 ilk Err 0&lt;BR /&gt;FIA00 crc Err 0&lt;BR /&gt;FIA00 seq Err 0&lt;BR /&gt;FIA01 Rx Err 0&lt;BR /&gt;FIA01 ilk Err 0&lt;BR /&gt;FIA01 crc Err 0&lt;BR /&gt;FIA01 seq Err 0&lt;BR /&gt;FIA10 Rx Err 0&lt;BR /&gt;FIA10 ilk Err 0&lt;BR /&gt;FIA10 crc Err 0&lt;BR /&gt;FIA10 seq Err 0&lt;BR /&gt;FIA11 Rx Err 0&lt;BR /&gt;FIA11 ilk Err 0&lt;BR /&gt;FIA11 crc Err 0&lt;BR /&gt;FIA11 seq Err 0&lt;BR /&gt;FIA00 crc1 Err 0&lt;BR /&gt;FIA00 crc2 Err 0&lt;BR /&gt;FIA01 crc1 Err 0&lt;BR /&gt;FIA01 crc2 Err 0&lt;BR /&gt;FIA10 crc1 Err 0&lt;BR /&gt;FIA10 crc2 Err 0&lt;BR /&gt;FIA11 crc1 Err 0&lt;BR /&gt;FIA11 crc2 Err 0&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;RP/0/RSP0/CPU0:NS3#show controller fabric fia drop in location 0/0/CPU0&lt;BR /&gt;Fri Nov 4 17:38:33.515 CET&lt;/P&gt;&lt;P&gt;********** FIA-0 **********&lt;BR /&gt;Category: in_drop-0&lt;BR /&gt;From Spaui Drop-0 0&lt;BR /&gt;accpt tbl-0 0&lt;BR /&gt;ctl len-0 0&lt;BR /&gt;short pkt-0 0&lt;BR /&gt;max pkt len-0 0&lt;BR /&gt;min pkt len-0 0&lt;BR /&gt;From Spaui Drop-1 0&lt;BR /&gt;accpt tbl-1 0&lt;BR /&gt;ctl len-1 0&lt;BR /&gt;short pkt-1 0&lt;BR /&gt;max pkt len-1 0&lt;BR /&gt;min pkt len-1 0&lt;BR /&gt;Tail drp 0&lt;BR /&gt;Vqi drp 0&lt;BR /&gt;Header parsing drp 0&lt;BR /&gt;pw to ni drp 0&lt;BR /&gt;ni from pw drp 0&lt;BR /&gt;sp0 crc err 0&lt;BR /&gt;sp0 bad align 0&lt;BR /&gt;sp0 bad code 0&lt;BR /&gt;sp0 align fail 3&lt;BR /&gt;sp0 prot err 0&lt;BR /&gt;sp1 crc err 2&lt;BR /&gt;sp1 bad align 0&lt;BR /&gt;sp1 bad code 1&lt;BR /&gt;sp1 align fail 3&lt;BR /&gt;sp1 prot err 0&lt;/P&gt;&lt;P&gt;********** FIA-1 **********&lt;BR /&gt;Category: in_drop-1&lt;BR /&gt;From Spaui Drop-0 0&lt;BR /&gt;accpt tbl-0 0&lt;BR /&gt;ctl len-0 0&lt;BR /&gt;short pkt-0 0&lt;BR /&gt;max pkt len-0 0&lt;BR /&gt;min pkt len-0 0&lt;BR /&gt;From Spaui Drop-1 0&lt;BR /&gt;accpt tbl-1 0&lt;BR /&gt;ctl len-1 0&lt;BR /&gt;short pkt-1 0&lt;BR /&gt;max pkt len-1 0&lt;BR /&gt;min pkt len-1 0&lt;BR /&gt;Tail drp 0&lt;BR /&gt;Vqi drp 0&lt;BR /&gt;Header parsing drp 0&lt;BR /&gt;pw to ni drp 0&lt;BR /&gt;ni from pw drp 0&lt;BR /&gt;sp0 crc err 0&lt;BR /&gt;sp0 bad align 0&lt;BR /&gt;sp0 bad code 0&lt;BR /&gt;sp0 align fail 3&lt;BR /&gt;sp0 prot err 0&lt;BR /&gt;sp1 crc err 12&lt;BR /&gt;sp1 bad align 0&lt;BR /&gt;sp1 bad code 7&lt;BR /&gt;sp1 align fail 3&lt;BR /&gt;sp1 prot err 3&lt;/P&gt;&lt;P&gt;********** FIA-2 **********&lt;BR /&gt;Category: in_drop-2&lt;BR /&gt;From Spaui Drop-0 0&lt;BR /&gt;accpt tbl-0 0&lt;BR /&gt;ctl len-0 0&lt;BR /&gt;short pkt-0 0&lt;BR /&gt;max pkt len-0 0&lt;BR /&gt;min pkt len-0 0&lt;BR /&gt;From Spaui Drop-1 0&lt;BR /&gt;accpt tbl-1 0&lt;BR /&gt;ctl len-1 0&lt;BR /&gt;short pkt-1 0&lt;BR /&gt;max pkt len-1 0&lt;BR /&gt;min pkt len-1 0&lt;BR /&gt;Tail drp 0&lt;BR /&gt;Vqi drp 0&lt;BR /&gt;Header parsing drp 0&lt;BR /&gt;pw to ni drp 0&lt;BR /&gt;ni from pw drp 0&lt;BR /&gt;sp0 crc err 0&lt;BR /&gt;sp0 bad align 0&lt;BR /&gt;sp0 bad code 0&lt;BR /&gt;sp0 align fail 3&lt;BR /&gt;sp0 prot err 0&lt;BR /&gt;sp1 crc err 0&lt;BR /&gt;sp1 bad align 0&lt;BR /&gt;sp1 bad code 0&lt;BR /&gt;sp1 align fail 3&lt;BR /&gt;sp1 prot err 0&lt;/P&gt;&lt;P&gt;********** FIA-3 **********&lt;BR /&gt;Category: in_drop-3&lt;BR /&gt;From Spaui Drop-0 0&lt;BR /&gt;accpt tbl-0 0&lt;BR /&gt;ctl len-0 0&lt;BR /&gt;short pkt-0 0&lt;BR /&gt;max pkt len-0 0&lt;BR /&gt;min pkt len-0 0&lt;BR /&gt;From Spaui Drop-1 0&lt;BR /&gt;accpt tbl-1 0&lt;BR /&gt;ctl len-1 0&lt;BR /&gt;short pkt-1 0&lt;BR /&gt;max pkt len-1 0&lt;BR /&gt;min pkt len-1 0&lt;BR /&gt;Tail drp 0&lt;BR /&gt;Vqi drp 0&lt;BR /&gt;Header parsing drp 0&lt;BR /&gt;pw to ni drp 0&lt;BR /&gt;ni from pw drp 0&lt;BR /&gt;sp0 crc err 25&lt;BR /&gt;sp0 bad align 0&lt;BR /&gt;sp0 bad code 14&lt;BR /&gt;sp0 align fail 3&lt;BR /&gt;sp0 prot err 8&lt;BR /&gt;sp1 crc err 0&lt;BR /&gt;sp1 bad align 0&lt;BR /&gt;sp1 bad code 1&lt;BR /&gt;sp1 align fail 3&lt;BR /&gt;sp1 prot err 0&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;RP/0/RSP0/CPU0:NS3#show controller fabric fia q-depth location 0/0/CPU0&lt;BR /&gt;Fri Nov 4 17:39:14.798 CET&lt;/P&gt;&lt;P&gt;********** FIA-0 **********&lt;BR /&gt;Category: q_stats_a-0&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;********** FIA-0 **********&lt;BR /&gt;Category: q_stats_b-0&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;********** FIA-1 **********&lt;BR /&gt;Category: q_stats_a-1&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;BR /&gt;323 0 2 92 LC2_1_3&lt;/P&gt;&lt;P&gt;********** FIA-1 **********&lt;BR /&gt;Category: q_stats_b-1&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;********** FIA-2 **********&lt;BR /&gt;Category: q_stats_a-2&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;********** FIA-2 **********&lt;BR /&gt;Category: q_stats_b-2&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;********** FIA-3 **********&lt;BR /&gt;Category: q_stats_a-3&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;********** FIA-3 **********&lt;BR /&gt;Category: q_stats_b-3&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;RP/0/RSP1/CPU0:W4A#show controller np ports all location 0/0/CPU0&lt;BR /&gt;Fri Nov 4 16:24:44.096 CET&lt;/P&gt;&lt;P&gt;Node: 0/0/CPU0:&lt;BR /&gt;----------------------------------------------------------------&lt;/P&gt;&lt;P&gt;CPX NP Bridge Fia Ports&lt;BR /&gt;--- -- ------ --- ----------------------------------------------&lt;BR /&gt;0 0 0 0 HundredGigE0/0/0/1&lt;BR /&gt;0 1 0 1 HundredGigE0/0/0/1&lt;BR /&gt;1 2 1 2 HundredGigE0/0/0/0&lt;BR /&gt;1 3 1 3 HundredGigE0/0/0/0&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Then with the command below I identified that in bridge 1 (the one that controls the offending port) there are various errors:&lt;/P&gt;&lt;P&gt;RP/0/RSP1/CPU0:W4A#show controllers fabric fia bridge stats location 0/0/CPU0&lt;BR /&gt;Fri Nov 4 16:46:50.210 CET&lt;/P&gt;&lt;P&gt;********** FIA-0 **********&lt;BR /&gt;Category: bridge_in-0&lt;BR /&gt;To FIA0 L-0 1975908298&lt;BR /&gt;To FIA0 L-1 22657962790&lt;BR /&gt;To FIA1 L-0 25593342316&lt;BR /&gt;To FIA1 L-1 2394174402&lt;BR /&gt;Frm NPU ilk 52621387810&lt;BR /&gt;Frm NPU Pkt 52621387812&lt;BR /&gt;MC Ch0 Pkt drp 0&lt;BR /&gt;MC Ch1 Pkt drp 0&lt;BR /&gt;MC Ch2 Pkt drp 0&lt;BR /&gt;MC Ch3 Pkt drp 0&lt;BR /&gt;FIA00 Tx Err 0&lt;BR /&gt;FIA01 Tx Err 0&lt;BR /&gt;FIA10 Tx Err 0&lt;BR /&gt;FIA11 Tx Err 0&lt;BR /&gt;NP Err1 Cnt 0&lt;BR /&gt;NP Err2 Cnt 0&lt;BR /&gt;NP Err3 Cnt 0&lt;BR /&gt;NP Err4 Cnt 0&lt;BR /&gt;NP WrdSync1 0&lt;BR /&gt;NP WrdSync2 0&lt;BR /&gt;NP WrdSync3 0&lt;BR /&gt;NP WrdSync4 0&lt;BR /&gt;NP WrdSync5 0&lt;BR /&gt;NP WrdSync6 0&lt;BR /&gt;NP MFrm Err1 0&lt;BR /&gt;NP MFrm Err2 0&lt;BR /&gt;NP MFrm Err3 0&lt;BR /&gt;NP MFrm Err4 0&lt;BR /&gt;NP MFrm Err5 0&lt;BR /&gt;NP MFrm Err6 0&lt;BR /&gt;NP BType Err1 0&lt;BR /&gt;NP BType Err2 0&lt;BR /&gt;NP BType Err3 0&lt;BR /&gt;NP BType Err4 0&lt;BR /&gt;NP BType Err5 0&lt;BR /&gt;NP BType Err6 0&lt;BR /&gt;NP MFrmSync1 0&lt;BR /&gt;NP MFrmSync2 0&lt;BR /&gt;NP MFrmSync3 0&lt;BR /&gt;NP MFrmSync4 0&lt;BR /&gt;NP MFrmSync5 0&lt;BR /&gt;NP MFrmSync6 0&lt;BR /&gt;NP MFrmLn Err1 0&lt;BR /&gt;NP MFrmLn Err2 0&lt;BR /&gt;NP MFrmLn Err3 0&lt;BR /&gt;NP MFrmLn Err4 0&lt;BR /&gt;NP MFrmLn Err5 0&lt;BR /&gt;NP MFrmLn Err6 0&lt;/P&gt;&lt;P&gt;********** FIA-0 **********&lt;BR /&gt;Category: bridge_eg-0&lt;BR /&gt;FIA0 L-0 ilk 18551480573&lt;BR /&gt;FIA0 L-1 ilk 18151690715&lt;BR /&gt;FIA1 L-0 ilk 704245493002&lt;BR /&gt;FIA1 L-1 ilk 18668799906&lt;BR /&gt;FIA0 L-0 Pkt 18551480576&lt;BR /&gt;FIA0 L-1 Pkt 18151690718&lt;BR /&gt;FIA1 L-0 Pkt 704245493007&lt;BR /&gt;FIA1 L-1 Pkt 18668799908&lt;BR /&gt;To NPU 759617464248&lt;BR /&gt;UC LO Pkt ctr 758964674469&lt;BR /&gt;UC HI Pkt ctr 16613759&lt;BR /&gt;MC LO Pkt ctr 1003120&lt;BR /&gt;MC HI Pkt ctr 635172902&lt;BR /&gt;UC LO Pkt drp 0&lt;BR /&gt;UC HI Pkt drp 0&lt;BR /&gt;MC LO Pkt drp 0&lt;BR /&gt;MC HI Pkt drp 0&lt;BR /&gt;FIA00 Pkt drp 0&lt;BR /&gt;FIA01 Pkt drp 0&lt;BR /&gt;FIA10 Pkt drp 0&lt;BR /&gt;FIA11 Pkt drp 0&lt;BR /&gt;NPU Err Cnt 0&lt;BR /&gt;FIA00 Rx Err 0&lt;BR /&gt;FIA00 ilk Err 0&lt;BR /&gt;FIA00 crc Err 0&lt;BR /&gt;FIA00 seq Err 0&lt;BR /&gt;FIA01 Rx Err 0&lt;BR /&gt;FIA01 ilk Err 0&lt;BR /&gt;FIA01 crc Err 0&lt;BR /&gt;FIA01 seq Err 0&lt;BR /&gt;FIA10 Rx Err 0&lt;BR /&gt;FIA10 ilk Err 0&lt;BR /&gt;FIA10 crc Err 0&lt;BR /&gt;FIA10 seq Err 0&lt;BR /&gt;FIA11 Rx Err 0&lt;BR /&gt;FIA11 ilk Err 0&lt;BR /&gt;FIA11 crc Err 0&lt;BR /&gt;FIA11 seq Err 0&lt;BR /&gt;FIA00 crc1 Err 0&lt;BR /&gt;FIA00 crc2 Err 0&lt;BR /&gt;FIA01 crc1 Err 0&lt;BR /&gt;FIA01 crc2 Err 0&lt;BR /&gt;FIA10 crc1 Err 0&lt;BR /&gt;FIA10 crc2 Err 0&lt;BR /&gt;FIA11 crc1 Err 0&lt;BR /&gt;FIA11 crc2 Err 0&lt;/P&gt;&lt;P&gt;********** FIA-1 **********&lt;BR /&gt;Category: bridge_in-1&lt;BR /&gt;To FIA0 L-0 1897378903970&lt;BR /&gt;To FIA0 L-1 716307026477&lt;BR /&gt;To FIA1 L-0 14725384592&lt;BR /&gt;To FIA1 L-1 796301087214&lt;BR /&gt;Frm NPU ilk 3424712402254&lt;BR /&gt;Frm NPU Pkt 3424712402257&lt;BR /&gt;MC Ch0 Pkt drp 0&lt;BR /&gt;MC Ch1 Pkt drp 0&lt;BR /&gt;MC Ch2 Pkt drp 0&lt;BR /&gt;MC Ch3 Pkt drp 0&lt;BR /&gt;FIA00 Tx Err 0&lt;BR /&gt;FIA01 Tx Err 0&lt;BR /&gt;FIA10 Tx Err 0&lt;BR /&gt;FIA11 Tx Err 0&lt;BR /&gt;NP Err1 Cnt 0&lt;BR /&gt;NP Err2 Cnt 0&lt;BR /&gt;NP Err3 Cnt 0&lt;BR /&gt;NP Err4 Cnt 0&lt;BR /&gt;NP WrdSync1 0&lt;BR /&gt;NP WrdSync2 0&lt;BR /&gt;NP WrdSync3 0&lt;BR /&gt;NP WrdSync4 0&lt;BR /&gt;NP WrdSync5 0&lt;BR /&gt;NP WrdSync6 0&lt;BR /&gt;NP MFrm Err1 0&lt;BR /&gt;NP MFrm Err2 0&lt;BR /&gt;NP MFrm Err3 0&lt;BR /&gt;NP MFrm Err4 0&lt;BR /&gt;NP MFrm Err5 0&lt;BR /&gt;NP MFrm Err6 0&lt;BR /&gt;NP BType Err1 0&lt;BR /&gt;NP BType Err2 0&lt;BR /&gt;NP BType Err3 0&lt;BR /&gt;NP BType Err4 0&lt;BR /&gt;NP BType Err5 0&lt;BR /&gt;NP BType Err6 0&lt;BR /&gt;NP MFrmSync1 0&lt;BR /&gt;NP MFrmSync2 0&lt;BR /&gt;NP MFrmSync3 0&lt;BR /&gt;NP MFrmSync4 0&lt;BR /&gt;NP MFrmSync5 0&lt;BR /&gt;NP MFrmSync6 0&lt;BR /&gt;NP MFrmLn Err1 0&lt;BR /&gt;NP MFrmLn Err2 0&lt;BR /&gt;NP MFrmLn Err3 0&lt;BR /&gt;NP MFrmLn Err4 0&lt;BR /&gt;NP MFrmLn Err5 0&lt;BR /&gt;NP MFrmLn Err6 0&lt;/P&gt;&lt;P&gt;********** FIA-1 **********&lt;BR /&gt;Category: bridge_eg-1&lt;BR /&gt;FIA0 L-0 ilk 1745875069&lt;BR /&gt;FIA0 L-1 ilk 1430103512&lt;BR /&gt;FIA1 L-0 ilk 38157078790&lt;BR /&gt;FIA1 L-1 ilk 1424658053&lt;BR /&gt;FIA0 L-0 Pkt 1745875070&lt;BR /&gt;FIA0 L-1 Pkt 1430103513&lt;BR /&gt;FIA1 L-0 Pkt 38157078795&lt;BR /&gt;FIA1 L-1 Pkt 1424615986&lt;BR /&gt;To NPU 42757673372&lt;BR /&gt;UC LO Pkt ctr 42375120096&lt;BR /&gt;UC HI Pkt ctr 982848&lt;BR /&gt;MC LO Pkt ctr 91752&lt;BR /&gt;MC HI Pkt ctr 381478679&lt;BR /&gt;UC LO Pkt drp 0&lt;BR /&gt;UC HI Pkt drp 0&lt;BR /&gt;MC LO Pkt drp 0&lt;BR /&gt;MC HI Pkt drp 0&lt;BR /&gt;FIA00 Pkt drp 0&lt;BR /&gt;FIA01 Pkt drp 0&lt;BR /&gt;FIA10 Pkt drp 0&lt;BR /&gt;FIA11 Pkt drp 0&lt;BR /&gt;NPU Err Cnt 0&lt;BR /&gt;FIA00 Rx Err 0&lt;BR /&gt;FIA00 ilk Err 0&lt;BR /&gt;FIA00 crc Err 0&lt;BR /&gt;FIA00 seq Err 0&lt;BR /&gt;FIA01 Rx Err 0&lt;BR /&gt;FIA01 ilk Err 0&lt;BR /&gt;FIA01 crc Err 0&lt;BR /&gt;FIA01 seq Err 0&lt;BR /&gt;FIA10 Rx Err 0&lt;BR /&gt;FIA10 ilk Err 0&lt;BR /&gt;FIA10 crc Err 0&lt;BR /&gt;FIA10 seq Err 0&lt;BR /&gt;FIA11 Rx Err 52212&lt;BR /&gt;FIA11 ilk Err 365441&lt;BR /&gt;FIA11 crc Err 3786383512&lt;BR /&gt;FIA11 seq Err 1&lt;BR /&gt;FIA00 crc1 Err 0&lt;BR /&gt;FIA00 crc2 Err 0&lt;BR /&gt;FIA01 crc1 Err 0&lt;BR /&gt;FIA01 crc2 Err 0&lt;BR /&gt;FIA10 crc1 Err 0&lt;BR /&gt;FIA10 crc2 Err 0&lt;BR /&gt;FIA11 crc1 Err 3783754038&lt;BR /&gt;FIA11 crc2 Err 0&lt;/P&gt;&lt;P&gt;RP/0/RSP1/CPU0:W4A#show controller fabric fia drop in location 0/0/CPU0&lt;BR /&gt;Fri Nov 4 17:00:32.660 CET&lt;/P&gt;&lt;P&gt;********** FIA-0 **********&lt;BR /&gt;Category: in_drop-0&lt;BR /&gt;From Spaui Drop-0 0&lt;BR /&gt;accpt tbl-0 0&lt;BR /&gt;ctl len-0 0&lt;BR /&gt;short pkt-0 0&lt;BR /&gt;max pkt len-0 0&lt;BR /&gt;min pkt len-0 0&lt;BR /&gt;From Spaui Drop-1 0&lt;BR /&gt;accpt tbl-1 0&lt;BR /&gt;ctl len-1 0&lt;BR /&gt;short pkt-1 0&lt;BR /&gt;max pkt len-1 0&lt;BR /&gt;min pkt len-1 0&lt;BR /&gt;Tail drp 0&lt;BR /&gt;Vqi drp 0&lt;BR /&gt;Header parsing drp 0&lt;BR /&gt;pw to ni drp 0&lt;BR /&gt;ni from pw drp 0&lt;BR /&gt;sp0 crc err 0&lt;BR /&gt;sp0 bad align 0&lt;BR /&gt;sp0 bad code 0&lt;BR /&gt;sp0 align fail 3&lt;BR /&gt;sp0 prot err 0&lt;BR /&gt;sp1 crc err 16&lt;BR /&gt;sp1 bad align 0&lt;BR /&gt;sp1 bad code 16&lt;BR /&gt;sp1 align fail 3&lt;BR /&gt;sp1 prot err 3&lt;/P&gt;&lt;P&gt;********** FIA-1 **********&lt;BR /&gt;Category: in_drop-1&lt;BR /&gt;From Spaui Drop-0 0&lt;BR /&gt;accpt tbl-0 0&lt;BR /&gt;ctl len-0 0&lt;BR /&gt;short pkt-0 0&lt;BR /&gt;max pkt len-0 0&lt;BR /&gt;min pkt len-0 0&lt;BR /&gt;From Spaui Drop-1 0&lt;BR /&gt;accpt tbl-1 0&lt;BR /&gt;ctl len-1 0&lt;BR /&gt;short pkt-1 0&lt;BR /&gt;max pkt len-1 0&lt;BR /&gt;min pkt len-1 0&lt;BR /&gt;Tail drp 0&lt;BR /&gt;Vqi drp 0&lt;BR /&gt;Header parsing drp 0&lt;BR /&gt;pw to ni drp 0&lt;BR /&gt;ni from pw drp 0&lt;BR /&gt;sp0 crc err 1&lt;BR /&gt;sp0 bad align 0&lt;BR /&gt;sp0 bad code 0&lt;BR /&gt;sp0 align fail 3&lt;BR /&gt;sp0 prot err 0&lt;BR /&gt;sp1 crc err 0&lt;BR /&gt;sp1 bad align 0&lt;BR /&gt;sp1 bad code 0&lt;BR /&gt;sp1 align fail 3&lt;BR /&gt;sp1 prot err 0&lt;/P&gt;&lt;P&gt;********** FIA-2 **********&lt;BR /&gt;Category: in_drop-2&lt;BR /&gt;From Spaui Drop-0 0&lt;BR /&gt;accpt tbl-0 0&lt;BR /&gt;ctl len-0 0&lt;BR /&gt;short pkt-0 0&lt;BR /&gt;max pkt len-0 0&lt;BR /&gt;min pkt len-0 0&lt;BR /&gt;From Spaui Drop-1 0&lt;BR /&gt;accpt tbl-1 0&lt;BR /&gt;ctl len-1 0&lt;BR /&gt;short pkt-1 0&lt;BR /&gt;max pkt len-1 0&lt;BR /&gt;min pkt len-1 0&lt;BR /&gt;Tail drp 103685&lt;BR /&gt;Vqi drp 0&lt;BR /&gt;Header parsing drp 0&lt;BR /&gt;pw to ni drp 0&lt;BR /&gt;ni from pw drp 0&lt;BR /&gt;sp0 crc err 0&lt;BR /&gt;sp0 bad align 0&lt;BR /&gt;sp0 bad code 0&lt;BR /&gt;sp0 align fail 3&lt;BR /&gt;sp0 prot err 0&lt;BR /&gt;sp1 crc err 0&lt;BR /&gt;sp1 bad align 0&lt;BR /&gt;sp1 bad code 0&lt;BR /&gt;sp1 align fail 3&lt;BR /&gt;sp1 prot err 0&lt;/P&gt;&lt;P&gt;********** FIA-3 **********&lt;BR /&gt;Category: in_drop-3&lt;BR /&gt;From Spaui Drop-0 0&lt;BR /&gt;accpt tbl-0 0&lt;BR /&gt;ctl len-0 0&lt;BR /&gt;short pkt-0 0&lt;BR /&gt;max pkt len-0 0&lt;BR /&gt;min pkt len-0 0&lt;BR /&gt;From Spaui Drop-1 0&lt;BR /&gt;accpt tbl-1 0&lt;BR /&gt;ctl len-1 0&lt;BR /&gt;short pkt-1 0&lt;BR /&gt;max pkt len-1 0&lt;BR /&gt;min pkt len-1 0&lt;BR /&gt;Tail drp 0&lt;BR /&gt;Vqi drp 0&lt;BR /&gt;Header parsing drp 0&lt;BR /&gt;pw to ni drp 0&lt;BR /&gt;ni from pw drp 0&lt;BR /&gt;sp0 crc err 0&lt;BR /&gt;sp0 bad align 0&lt;BR /&gt;sp0 bad code 0&lt;BR /&gt;sp0 align fail 3&lt;BR /&gt;sp0 prot err 0&lt;BR /&gt;sp1 crc err 7&lt;BR /&gt;sp1 bad align 0&lt;BR /&gt;sp1 bad code 4&lt;BR /&gt;sp1 align fail 3&lt;BR /&gt;sp1 prot err 0&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;RP/0/RSP1/CPU0:W4A#show controller fabric fia q-depth location 0/0/CPU0&lt;BR /&gt;Fri Nov 4 17:01:19.200 CET&lt;/P&gt;&lt;P&gt;********** FIA-0 **********&lt;BR /&gt;Category: q_stats_a-0&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;********** FIA-0 **********&lt;BR /&gt;Category: q_stats_b-0&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;********** FIA-1 **********&lt;BR /&gt;Category: q_stats_a-1&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;********** FIA-1 **********&lt;BR /&gt;Category: q_stats_b-1&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;********** FIA-2 **********&lt;BR /&gt;Category: q_stats_a-2&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;********** FIA-2 **********&lt;BR /&gt;Category: q_stats_b-2&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;********** FIA-3 **********&lt;BR /&gt;Category: q_stats_a-3&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;BR /&gt;312 0 2 1450 LC2_0_0&lt;/P&gt;&lt;P&gt;********** FIA-3 **********&lt;BR /&gt;Category: q_stats_b-3&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Finally I paste the output of the same 4 commands from the machine that has no problems:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;RP/0/RSP0/CPU0:NS3#show controller np ports all location 0/0/CPU0&lt;BR /&gt;Fri Nov 4 17:37:30.510 CET&lt;/P&gt;&lt;P&gt;Node: 0/0/CPU0:&lt;BR /&gt;----------------------------------------------------------------&lt;/P&gt;&lt;P&gt;CPX NP Bridge Fia Ports&lt;BR /&gt;--- -- ------ --- ----------------------------------------------&lt;BR /&gt;0 0 0 0 HundredGigE0/0/0/1&lt;BR /&gt;0 1 0 1 HundredGigE0/0/0/1&lt;BR /&gt;1 2 1 2 HundredGigE0/0/0/0&lt;BR /&gt;1 3 1 3 HundredGigE0/0/0/0&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;RP/0/RSP0/CPU0:NS3#show controllers fabric fia bridge stats location 0/0/CPU0&lt;BR /&gt;Fri Nov 4 17:37:59.049 CET&lt;/P&gt;&lt;P&gt;********** FIA-0 **********&lt;BR /&gt;Category: bridge_in-0&lt;BR /&gt;To FIA0 L-0 27477332927&lt;BR /&gt;To FIA0 L-1 27847393105&lt;BR /&gt;To FIA1 L-0 27774090133&lt;BR /&gt;To FIA1 L-1 28387156842&lt;BR /&gt;Frm NPU ilk 111485973012&lt;BR /&gt;Frm NPU Pkt 111485973014&lt;BR /&gt;MC Ch0 Pkt drp 0&lt;BR /&gt;MC Ch1 Pkt drp 0&lt;BR /&gt;MC Ch2 Pkt drp 0&lt;BR /&gt;MC Ch3 Pkt drp 0&lt;BR /&gt;FIA00 Tx Err 0&lt;BR /&gt;FIA01 Tx Err 0&lt;BR /&gt;FIA10 Tx Err 0&lt;BR /&gt;FIA11 Tx Err 0&lt;BR /&gt;NP Err1 Cnt 0&lt;BR /&gt;NP Err2 Cnt 0&lt;BR /&gt;NP Err3 Cnt 0&lt;BR /&gt;NP Err4 Cnt 0&lt;BR /&gt;NP WrdSync1 0&lt;BR /&gt;NP WrdSync2 0&lt;BR /&gt;NP WrdSync3 0&lt;BR /&gt;NP WrdSync4 0&lt;BR /&gt;NP WrdSync5 0&lt;BR /&gt;NP WrdSync6 0&lt;BR /&gt;NP MFrm Err1 0&lt;BR /&gt;NP MFrm Err2 0&lt;BR /&gt;NP MFrm Err3 0&lt;BR /&gt;NP MFrm Err4 0&lt;BR /&gt;NP MFrm Err5 0&lt;BR /&gt;NP MFrm Err6 0&lt;BR /&gt;NP BType Err1 0&lt;BR /&gt;NP BType Err2 0&lt;BR /&gt;NP BType Err3 0&lt;BR /&gt;NP BType Err4 0&lt;BR /&gt;NP BType Err5 0&lt;BR /&gt;NP BType Err6 0&lt;BR /&gt;NP MFrmSync1 0&lt;BR /&gt;NP MFrmSync2 0&lt;BR /&gt;NP MFrmSync3 0&lt;BR /&gt;NP MFrmSync4 0&lt;BR /&gt;NP MFrmSync5 0&lt;BR /&gt;NP MFrmSync6 0&lt;BR /&gt;NP MFrmLn Err1 0&lt;BR /&gt;NP MFrmLn Err2 0&lt;BR /&gt;NP MFrmLn Err3 0&lt;BR /&gt;NP MFrmLn Err4 0&lt;BR /&gt;NP MFrmLn Err5 0&lt;BR /&gt;NP MFrmLn Err6 0&lt;/P&gt;&lt;P&gt;********** FIA-0 **********&lt;BR /&gt;Category: bridge_eg-0&lt;BR /&gt;FIA0 L-0 ilk 57343383331&lt;BR /&gt;FIA0 L-1 ilk 56875518953&lt;BR /&gt;FIA1 L-0 ilk 57318428927&lt;BR /&gt;FIA1 L-1 ilk 57342623474&lt;BR /&gt;FIA0 L-0 Pkt 57343383334&lt;BR /&gt;FIA0 L-1 Pkt 56875518958&lt;BR /&gt;FIA1 L-0 Pkt 57318428932&lt;BR /&gt;FIA1 L-1 Pkt 57342623478&lt;BR /&gt;To NPU 228879954725&lt;BR /&gt;UC LO Pkt ctr 228152056244&lt;BR /&gt;UC HI Pkt ctr 79434304&lt;BR /&gt;MC LO Pkt ctr 240256&lt;BR /&gt;MC HI Pkt ctr 648223921&lt;BR /&gt;UC LO Pkt drp 0&lt;BR /&gt;UC HI Pkt drp 0&lt;BR /&gt;MC LO Pkt drp 0&lt;BR /&gt;MC HI Pkt drp 0&lt;BR /&gt;FIA00 Pkt drp 0&lt;BR /&gt;FIA01 Pkt drp 0&lt;BR /&gt;FIA10 Pkt drp 0&lt;BR /&gt;FIA11 Pkt drp 0&lt;BR /&gt;NPU Err Cnt 0&lt;BR /&gt;FIA00 Rx Err 0&lt;BR /&gt;FIA00 ilk Err 0&lt;BR /&gt;FIA00 crc Err 0&lt;BR /&gt;FIA00 seq Err 0&lt;BR /&gt;FIA01 Rx Err 0&lt;BR /&gt;FIA01 ilk Err 0&lt;BR /&gt;FIA01 crc Err 0&lt;BR /&gt;FIA01 seq Err 0&lt;BR /&gt;FIA10 Rx Err 0&lt;BR /&gt;FIA10 ilk Err 0&lt;BR /&gt;FIA10 crc Err 0&lt;BR /&gt;FIA10 seq Err 0&lt;BR /&gt;FIA11 Rx Err 0&lt;BR /&gt;FIA11 ilk Err 0&lt;BR /&gt;FIA11 crc Err 0&lt;BR /&gt;FIA11 seq Err 0&lt;BR /&gt;FIA00 crc1 Err 0&lt;BR /&gt;FIA00 crc2 Err 0&lt;BR /&gt;FIA01 crc1 Err 0&lt;BR /&gt;FIA01 crc2 Err 0&lt;BR /&gt;FIA10 crc1 Err 0&lt;BR /&gt;FIA10 crc2 Err 0&lt;BR /&gt;FIA11 crc1 Err 0&lt;BR /&gt;FIA11 crc2 Err 0&lt;/P&gt;&lt;P&gt;********** FIA-1 **********&lt;BR /&gt;Category: bridge_in-1&lt;BR /&gt;To FIA0 L-0 413523092710&lt;BR /&gt;To FIA0 L-1 408254651520&lt;BR /&gt;To FIA1 L-0 407426294052&lt;BR /&gt;To FIA1 L-1 1607159674927&lt;BR /&gt;Frm NPU ilk 2836363713215&lt;BR /&gt;Frm NPU Pkt 2836363713219&lt;BR /&gt;MC Ch0 Pkt drp 0&lt;BR /&gt;MC Ch1 Pkt drp 0&lt;BR /&gt;MC Ch2 Pkt drp 0&lt;BR /&gt;MC Ch3 Pkt drp 0&lt;BR /&gt;FIA00 Tx Err 0&lt;BR /&gt;FIA01 Tx Err 0&lt;BR /&gt;FIA10 Tx Err 0&lt;BR /&gt;FIA11 Tx Err 0&lt;BR /&gt;NP Err1 Cnt 0&lt;BR /&gt;NP Err2 Cnt 0&lt;BR /&gt;NP Err3 Cnt 0&lt;BR /&gt;NP Err4 Cnt 0&lt;BR /&gt;NP WrdSync1 0&lt;BR /&gt;NP WrdSync2 0&lt;BR /&gt;NP WrdSync3 0&lt;BR /&gt;NP WrdSync4 0&lt;BR /&gt;NP WrdSync5 0&lt;BR /&gt;NP WrdSync6 0&lt;BR /&gt;NP MFrm Err1 0&lt;BR /&gt;NP MFrm Err2 0&lt;BR /&gt;NP MFrm Err3 0&lt;BR /&gt;NP MFrm Err4 0&lt;BR /&gt;NP MFrm Err5 0&lt;BR /&gt;NP MFrm Err6 0&lt;BR /&gt;NP BType Err1 0&lt;BR /&gt;NP BType Err2 0&lt;BR /&gt;NP BType Err3 0&lt;BR /&gt;NP BType Err4 0&lt;BR /&gt;NP BType Err5 0&lt;BR /&gt;NP BType Err6 0&lt;BR /&gt;NP MFrmSync1 0&lt;BR /&gt;NP MFrmSync2 0&lt;BR /&gt;NP MFrmSync3 0&lt;BR /&gt;NP MFrmSync4 0&lt;BR /&gt;NP MFrmSync5 0&lt;BR /&gt;NP MFrmSync6 0&lt;BR /&gt;NP MFrmLn Err1 0&lt;BR /&gt;NP MFrmLn Err2 0&lt;BR /&gt;NP MFrmLn Err3 0&lt;BR /&gt;NP MFrmLn Err4 0&lt;BR /&gt;NP MFrmLn Err5 0&lt;BR /&gt;NP MFrmLn Err6 0&lt;/P&gt;&lt;P&gt;********** FIA-1 **********&lt;BR /&gt;Category: bridge_eg-1&lt;BR /&gt;FIA0 L-0 ilk 3400484549787&lt;BR /&gt;FIA0 L-1 ilk 105233491135&lt;BR /&gt;FIA1 L-0 ilk 102479840910&lt;BR /&gt;FIA1 L-1 ilk 101977545140&lt;BR /&gt;FIA0 L-0 Pkt 3400484549787&lt;BR /&gt;FIA0 L-1 Pkt 105233491136&lt;BR /&gt;FIA1 L-0 Pkt 102479840917&lt;BR /&gt;FIA1 L-1 Pkt 101977545143&lt;BR /&gt;To NPU 3710175426990&lt;BR /&gt;UC LO Pkt ctr 3709853180349&lt;BR /&gt;UC HI Pkt ctr 918672&lt;BR /&gt;MC LO Pkt ctr 95888&lt;BR /&gt;MC HI Pkt ctr 321232082&lt;BR /&gt;UC LO Pkt drp 0&lt;BR /&gt;UC HI Pkt drp 0&lt;BR /&gt;MC LO Pkt drp 0&lt;BR /&gt;MC HI Pkt drp 0&lt;BR /&gt;FIA00 Pkt drp 0&lt;BR /&gt;FIA01 Pkt drp 0&lt;BR /&gt;FIA10 Pkt drp 0&lt;BR /&gt;FIA11 Pkt drp 0&lt;BR /&gt;NPU Err Cnt 0&lt;BR /&gt;FIA00 Rx Err 0&lt;BR /&gt;FIA00 ilk Err 0&lt;BR /&gt;FIA00 crc Err 0&lt;BR /&gt;FIA00 seq Err 0&lt;BR /&gt;FIA01 Rx Err 0&lt;BR /&gt;FIA01 ilk Err 0&lt;BR /&gt;FIA01 crc Err 0&lt;BR /&gt;FIA01 seq Err 0&lt;BR /&gt;FIA10 Rx Err 0&lt;BR /&gt;FIA10 ilk Err 0&lt;BR /&gt;FIA10 crc Err 0&lt;BR /&gt;FIA10 seq Err 0&lt;BR /&gt;FIA11 Rx Err 0&lt;BR /&gt;FIA11 ilk Err 0&lt;BR /&gt;FIA11 crc Err 0&lt;BR /&gt;FIA11 seq Err 0&lt;BR /&gt;FIA00 crc1 Err 0&lt;BR /&gt;FIA00 crc2 Err 0&lt;BR /&gt;FIA01 crc1 Err 0&lt;BR /&gt;FIA01 crc2 Err 0&lt;BR /&gt;FIA10 crc1 Err 0&lt;BR /&gt;FIA10 crc2 Err 0&lt;BR /&gt;FIA11 crc1 Err 0&lt;BR /&gt;FIA11 crc2 Err 0&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;RP/0/RSP0/CPU0:NS3#show controller fabric fia drop in location 0/0/CPU0&lt;BR /&gt;Fri Nov 4 17:38:33.515 CET&lt;/P&gt;&lt;P&gt;********** FIA-0 **********&lt;BR /&gt;Category: in_drop-0&lt;BR /&gt;From Spaui Drop-0 0&lt;BR /&gt;accpt tbl-0 0&lt;BR /&gt;ctl len-0 0&lt;BR /&gt;short pkt-0 0&lt;BR /&gt;max pkt len-0 0&lt;BR /&gt;min pkt len-0 0&lt;BR /&gt;From Spaui Drop-1 0&lt;BR /&gt;accpt tbl-1 0&lt;BR /&gt;ctl len-1 0&lt;BR /&gt;short pkt-1 0&lt;BR /&gt;max pkt len-1 0&lt;BR /&gt;min pkt len-1 0&lt;BR /&gt;Tail drp 0&lt;BR /&gt;Vqi drp 0&lt;BR /&gt;Header parsing drp 0&lt;BR /&gt;pw to ni drp 0&lt;BR /&gt;ni from pw drp 0&lt;BR /&gt;sp0 crc err 0&lt;BR /&gt;sp0 bad align 0&lt;BR /&gt;sp0 bad code 0&lt;BR /&gt;sp0 align fail 3&lt;BR /&gt;sp0 prot err 0&lt;BR /&gt;sp1 crc err 2&lt;BR /&gt;sp1 bad align 0&lt;BR /&gt;sp1 bad code 1&lt;BR /&gt;sp1 align fail 3&lt;BR /&gt;sp1 prot err 0&lt;/P&gt;&lt;P&gt;********** FIA-1 **********&lt;BR /&gt;Category: in_drop-1&lt;BR /&gt;From Spaui Drop-0 0&lt;BR /&gt;accpt tbl-0 0&lt;BR /&gt;ctl len-0 0&lt;BR /&gt;short pkt-0 0&lt;BR /&gt;max pkt len-0 0&lt;BR /&gt;min pkt len-0 0&lt;BR /&gt;From Spaui Drop-1 0&lt;BR /&gt;accpt tbl-1 0&lt;BR /&gt;ctl len-1 0&lt;BR /&gt;short pkt-1 0&lt;BR /&gt;max pkt len-1 0&lt;BR /&gt;min pkt len-1 0&lt;BR /&gt;Tail drp 0&lt;BR /&gt;Vqi drp 0&lt;BR /&gt;Header parsing drp 0&lt;BR /&gt;pw to ni drp 0&lt;BR /&gt;ni from pw drp 0&lt;BR /&gt;sp0 crc err 0&lt;BR /&gt;sp0 bad align 0&lt;BR /&gt;sp0 bad code 0&lt;BR /&gt;sp0 align fail 3&lt;BR /&gt;sp0 prot err 0&lt;BR /&gt;sp1 crc err 12&lt;BR /&gt;sp1 bad align 0&lt;BR /&gt;sp1 bad code 7&lt;BR /&gt;sp1 align fail 3&lt;BR /&gt;sp1 prot err 3&lt;/P&gt;&lt;P&gt;********** FIA-2 **********&lt;BR /&gt;Category: in_drop-2&lt;BR /&gt;From Spaui Drop-0 0&lt;BR /&gt;accpt tbl-0 0&lt;BR /&gt;ctl len-0 0&lt;BR /&gt;short pkt-0 0&lt;BR /&gt;max pkt len-0 0&lt;BR /&gt;min pkt len-0 0&lt;BR /&gt;From Spaui Drop-1 0&lt;BR /&gt;accpt tbl-1 0&lt;BR /&gt;ctl len-1 0&lt;BR /&gt;short pkt-1 0&lt;BR /&gt;max pkt len-1 0&lt;BR /&gt;min pkt len-1 0&lt;BR /&gt;Tail drp 0&lt;BR /&gt;Vqi drp 0&lt;BR /&gt;Header parsing drp 0&lt;BR /&gt;pw to ni drp 0&lt;BR /&gt;ni from pw drp 0&lt;BR /&gt;sp0 crc err 0&lt;BR /&gt;sp0 bad align 0&lt;BR /&gt;sp0 bad code 0&lt;BR /&gt;sp0 align fail 3&lt;BR /&gt;sp0 prot err 0&lt;BR /&gt;sp1 crc err 0&lt;BR /&gt;sp1 bad align 0&lt;BR /&gt;sp1 bad code 0&lt;BR /&gt;sp1 align fail 3&lt;BR /&gt;sp1 prot err 0&lt;/P&gt;&lt;P&gt;********** FIA-3 **********&lt;BR /&gt;Category: in_drop-3&lt;BR /&gt;From Spaui Drop-0 0&lt;BR /&gt;accpt tbl-0 0&lt;BR /&gt;ctl len-0 0&lt;BR /&gt;short pkt-0 0&lt;BR /&gt;max pkt len-0 0&lt;BR /&gt;min pkt len-0 0&lt;BR /&gt;From Spaui Drop-1 0&lt;BR /&gt;accpt tbl-1 0&lt;BR /&gt;ctl len-1 0&lt;BR /&gt;short pkt-1 0&lt;BR /&gt;max pkt len-1 0&lt;BR /&gt;min pkt len-1 0&lt;BR /&gt;Tail drp 0&lt;BR /&gt;Vqi drp 0&lt;BR /&gt;Header parsing drp 0&lt;BR /&gt;pw to ni drp 0&lt;BR /&gt;ni from pw drp 0&lt;BR /&gt;sp0 crc err 25&lt;BR /&gt;sp0 bad align 0&lt;BR /&gt;sp0 bad code 14&lt;BR /&gt;sp0 align fail 3&lt;BR /&gt;sp0 prot err 8&lt;BR /&gt;sp1 crc err 0&lt;BR /&gt;sp1 bad align 0&lt;BR /&gt;sp1 bad code 1&lt;BR /&gt;sp1 align fail 3&lt;BR /&gt;sp1 prot err 0&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;RP/0/RSP0/CPU0:NS3#show controller fabric fia q-depth location 0/0/CPU0&lt;BR /&gt;Fri Nov 4 17:39:14.798 CET&lt;/P&gt;&lt;P&gt;********** FIA-0 **********&lt;BR /&gt;Category: q_stats_a-0&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;********** FIA-0 **********&lt;BR /&gt;Category: q_stats_b-0&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;********** FIA-1 **********&lt;BR /&gt;Category: q_stats_a-1&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;BR /&gt;323 0 2 92 LC2_1_3&lt;/P&gt;&lt;P&gt;********** FIA-1 **********&lt;BR /&gt;Category: q_stats_b-1&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;********** FIA-2 **********&lt;BR /&gt;Category: q_stats_a-2&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;********** FIA-2 **********&lt;BR /&gt;Category: q_stats_b-2&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;********** FIA-3 **********&lt;BR /&gt;Category: q_stats_a-3&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;********** FIA-3 **********&lt;BR /&gt;Category: q_stats_b-3&lt;BR /&gt;Voq ddr pri pktcnt Slot_FIA_NP&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 07 Nov 2022 09:13:56 GMT</pubDate>
      <guid>https://community.cisco.com/t5/routing/strange-issue-when-using-dual-esp100-in-combination-with-mip100/m-p/4716949#M374472</guid>
      <dc:creator>saul alonso ramos</dc:creator>
      <dc:date>2022-11-07T09:13:56Z</dc:date>
    </item>
  </channel>
</rss>

