topic Re: ASIC <--->CPU packet flow in Switching

ASIC <--->CPU packet flow

vijnaana47711 — Thu, 06 Jun 2019 08:09:02 GMT

Hi,

I would like to know if a CISCO switch uses DMA (Direct memory access) to copy a control packet (e.g OSPF) or a packet for which there is no entry in FIB to CPU? If not how does it happen?

I'm not familiar with the internal architecture/ packet path (ASIC <--->cpu), so any good reference docs on the same would be helpful too.

Thank you

Re: ASIC <--->CPU packet flow

Joseph W. Doherty — Thu, 06 Jun 2019 13:44:39 GMT

How it happens is likely considered proprietary information and also might vary between different hardware platforms.

Re: ASIC <--->CPU packet flow

vijnaana47711 — Thu, 06 Jun 2019 17:49:54 GMT

Hi Joseph,

I'm not looking for details, but just trying to get the big picture of whether DMA or some other mechanisms are used.

The answer need not be wrt a Cisco platform even.

Thank you

Re: ASIC <--->CPU packet flow

Scott Hodgdon — Thu, 06 Jun 2019 18:29:59 GMT

vijnaana47711,

Generally speaking, we will have special entries in the FIB for anything that is destined for the CPU. We would then have an interface connecting the CPU and forwarding engine over which this traffic would flow.

Cheers

Scott Hodgdon

Senior Technical Marketing Engineer

Enterprise Networking Group

Re: ASIC <--->CPU packet flow

vijnaana47711 — Thu, 06 Jun 2019 19:15:58 GMT

Hi Scott,

Can PCIe be one such interface and is DMA still being used by modern switches

with a switch fabric architecture?

Thank you

Re: ASIC <--->CPU packet flow

Scott Hodgdon — Thu, 06 Jun 2019 19:50:14 GMT

vijnaana47711,

Of the switches I have worked on (Cat 6K, Cat 9K) it has not been DMA. I cannot speak for all switches that Cisco has ever produced. You can find this kind of architectural information in the On-Demand Library of ciscolive.com (free for all to use) if you look for the BRKARC sessions for the individual switching platforms. For example, if you search for BRKARC-3468 you will find the Catalyst 6K session.

Cheers

Scott Hodgdon

Senior Technical Marketing Engineer

Enterprise Networking Group

Re: ASIC <--->CPU packet flow

vijnaana47711 — Fri, 07 Jun 2019 01:23:11 GMT

Thank you Scott!

That's the kind of reference I was looking for.

Re: ASIC <--->CPU packet flow

vijnaana47711 — Fri, 07 Jun 2019 02:38:38 GMT

Hi Scott,

One quick question. On going through the docs I got upon EOBC, but it talks of half duplex communication between Supervisor card and LC. I wonder if there's another such channel in the reverse direction for the CPU punt?

Thank you

Re: ASIC <--->CPU packet flow

Scott Hodgdon — Fri, 07 Jun 2019 14:00:12 GMT

vijnaana47711,

No data traffic uses the EOBC. This is just for system-level operations between Supervisor and LC in a Catalyst 6K (other switches may not have an EOBC). To get from LC to Supervisor, data traffic destined for the CPU will use either a fabric channel or the data bus depending on the LC type.

Cheers,

Scott Hodgdon

Senior Technical Marketing Engineer

Enterprise Networking Group

Re: ASIC <--->CPU packet flow

Joseph W. Doherty — Fri, 07 Jun 2019 16:00:00 GMT

Unclear what you're trying to find out. On any "powerful" router or switch you're likely have hardware that moves data about within the system without direct intervention of the main CPU, logically you would have something somewhat akin to DMA. The biggest difference might be the "other" hardware doing independent data movement likely is doing functions beyond just moving data too, i.e. it's more than what something like a PC DMA controller would do.

Scott suggests an excellent resource, Cisco Live papers, but even something like BRKARC-3468 when discussing "packet walks" is a higher level functional explanation, it generally doesn't get down into the weeds of how what is shown is actually accomplished.