On APIC-M2 where I have 2 phy fabric connections but at the GUI I have seen 4 phy interfaces, can someone help to explain the relationship or mapping between them. I am going to replace the APIC-M2 with APIC-M4 soon and need to move all the phy connections from APIC-M2 to APIC-M4, and there are 4 10g interfaces on APIC-M4. Thanks.
Leo
Accepted Solutions
Hi @a12288 ,
Firstly, your APIC M2 for which you've supplied the screenshot (tip - next time change/drag the size to full width) is fitted with a VIC 1455 or similar, shown as no 9 below and as bond0 on the APIC screenshot below (it's like yours, just my lab). The tricky bit is that eth2-1 and eth2-2 are ports 1 and 3 on the VIC. Ports 2 & 4 are not used. To see this mapping, you need to go to the CIMC and trace the MACs on the VICs (pic 3 & 4 below).
2 below is bond1 - consisting of eth1-1 and eth1-2
But back to your question - moving to the M4 should not be a problem except the bond1 interfaces will now be 10G - they should be installed in the mLom (3 below) and PCIe Riser 01 should have 2x10/25G SFPs or 2x10GBase-T ports - they will connect to two leaves
Hi @a12288 ,
Firstly, your APIC M2 for which you've supplied the screenshot (tip - next time change/drag the size to full width) is fitted with a VIC 1455 or similar, shown as no 9 below and as bond0 on the APIC screenshot below (it's like yours, just my lab). The tricky bit is that eth2-1 and eth2-2 are ports 1 and 3 on the VIC. Ports 2 & 4 are not used. To see this mapping, you need to go to the CIMC and trace the MACs on the VICs (pic 3 & 4 below).
2 below is bond1 - consisting of eth1-1 and eth1-2
But back to your question - moving to the M4 should not be a problem except the bond1 interfaces will now be 10G - they should be installed in the mLom (3 below) and PCIe Riser 01 should have 2x10/25G SFPs or 2x10GBase-T ports - they will connect to two leaves
