Hi,
I have 3 E1 bundled from same service provider and after a few months we had complaints regarding static noise heard over the the other line when we call someone from the office. This is random, at no particular time or day, but not always. When we check the E1 we see slip errors on all three E1 with the same amount of errors each.
I have searched here in the forums for solutions but all were suggesting different things, some say dont put "network-clock-participate" some says you need it. Some say to put the clocking on internal, some says on line (external).
I have 2 wic with 2 ports of E1. Here is my current config:
network-clock-participate wic 0
network-clock-participate wic 1
controller E1 0/0/0
clock source internal
pri-group timeslots 1-31
!
controller E1 0/0/1
clock source internal
pri-group timeslots 1-31
!
controller E1 0/1/0
clock source internal
pri-group timeslots 1-31
==================
router#sh network-clocks
Network Clock Configuration
---------------------------
Priority Clock Source Clock State Clock Type
10 Backplane GOOD PLL
Current Primary Clock Source
---------------------------
Priority Clock Source Clock State Clock Type
10 Backplane GOOD PLL
===================
router#sh controllers e1
E1 0/0/1 is up.
Applique type is Channelized E1 - balanced
No alarms detected.
alarm-trigger is not set
Version info FPGA Rev: 08121917, FPGA Type: PRK4
Framing is CRC4, Line Code is HDB3, Clock Source is Internal.
International Bit: 1, National Bits: 11111
Data in current interval (858 seconds elapsed):
0 Line Code Violations, 0 Path Code Violations
21 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
21 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
Total Data (last 2 15 minute intervals):
0 Line Code Violations, 0 Path Code Violations,
45 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins,
45 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
E1 0/1/0 is up.
Applique type is Channelized E1 - balanced
No alarms detected.
alarm-trigger is not set
Version info FPGA Rev: 08121917, FPGA Type: PRK4
Framing is CRC4, Line Code is HDB3, Clock Source is Internal.
International Bit: 1, National Bits: 11111
Data in current interval (858 seconds elapsed):
0 Line Code Violations, 0 Path Code Violations
21 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
21 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
Total Data (last 2 15 minute intervals):
0 Line Code Violations, 1 Path Code Violations,
45 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins,
46 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
