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The New Era of WAN – an ASIC innovation story

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Cisco Employee

Oct 20, 2020 is an inspirational date for many of us in networking industry to be proud of. It is the birthday of Cisco Catalyst 8500 Series Edge Platforms – one of the most powerful purpose-built SD-WAN Edge platforms ever, making up to 60Gbps throughput capacity from its turbocharged QFP3.0 engine. Quantum Flow Processor (QFP) ASIC innovation is true reflection of enterprise WAN transformation over the past decade.

 

March 4, 2008 was also a memorable date - Cisco virtually launched the Cisco ASR 1000 Series Router - the ancestor of Catalyst 8500 Series Edge Platforms via Social Media. Here is the snip of what was in the press release:

Market Trends and Issues

  • … double digit growth (11 percent) of remote branch offices. …
  • …TelePresence, IP voice and video conferencing, IPTV … create requirement for consistent and enhanced end user experience and prioritization of these applications over other network traffic. 
  • … More than 70 percent of the IDC survey respondents stated that they expect to increase bandwidth at corporate headquarters with 43 percent expecting increases of over 20 percent in the next 24 months…

<SNIP>

  • The Cisco ASR 1000 Series is powered by the new Cisco QuantumFlow Processor (QFP), the industry's most advanced networking chipset.
  • The Cisco QuantumFlow Processor can: 
    • process 24,000,000 instructions in the time it takes an average person to blink. 
    • provide equivalent processing power to 20 dual-core servers, using 10 times less space and 38,990 fewer kilowatt-hours per year

The 1st generation of QFP ASIC is made of a two chip complex – packet processor engine complex (PPE) and packet buffering/queueing/scheduling complex (BQS), provide processing capacity up to 40Gbps and provide consistent user experience for VoIP and TelePresence over congested WAN.

        

Picture-ppe.png        Picture-bqs.png

               PPE                     +                     BQS

The dynamics of enterprise WAN changed in 2013 (shown in the chart below), hybrid intelligent WAN became the trend of WAN architecture.

 

Picture3.pngPicture4.png

At that time, the 2nd generation QFP2.0 was introduced to meet the new challenges of enterprise WAN  – featuring a single chip with 64 PPE cores and 256 threads, and by cascading 4 x QFP2.0 together to form a mesh to provide up to 200Gbps aggregate system. The programmability and feature velocity of QFP2.0 provided incredible capability for application visibility, to allow enterprise to navigate through the rapid changing landscape of applications in the WAN.

 

Fast forward to 2020, the ‘New Normal’ puts SD-WAN in the fast lane. SD-WAN is quickly replacing the traditional VPN technologies, and merging the private & public WAN technologies, using a software-defined automation and analytics controller.

Picture5.png

Let me demystify it from the ASIC’s perspective. SD-WAN is becoming pervasive in every part of the enterprise networking – branch, DC, Colocation, Cloud, which drives the SD-WAN throughput demand to a new height. The majority of SD-WAN traffic is IPsec encrypted. On top of that, customers demand more application experience - prioritize business critical application, application aware routing, optimizes performance for SaaS applications, which further stressed out existing ASIC or Network Processor CPU capacity. The analytics demand drives the platforms to stream out large scale telemetry data and flow information to the controller and analytics engine.

 

The 3rd generation QFP3.0 was purpose-built for the SD-WAN world.

 

QFP3.0 was built with a new inline crypto-engine design provides a tremendous boost to the SD-WAN IPsec throughput up to 68Gbps with 1400-byte packet. QFP3.0 is designed to scale to 224 PPE processors and 896 simultaneous threads with 22nm technology and 6.8 Billion transistors in single ASIC to boost complex services performance such as deep packet inspection and flexible netflow. The outcome is that with the most common deployed SD-WAN services it can achieve the throughput up to 60Gbps with 1400-byte packet.

 

QFP3.0 is also designed in a highly scalable way to support 8,000 SD-WAN tunnels and 2,000,000 flows. It also doubles the amount of buffer scheduling queues to 256,000 to make it capable of address any large scale SD-WAN per-tunnel QoS deployment.

Picture6.png

With growing SD-WAN deployment in Colocation and DC, the connection speed for 40G and 100G ports is becoming a reality check. A colocation facility not only provides high-speed access into public and private cloud resources, but the center's geographical presence ensures that you can strategically select a facility in close proximity to end users. Hence, when coupled with Cisco SD-WAN, end user traffic is directed to the nearest colocation - where that traffic gets optimized, further secured and transmitted to its intended destination over a high-speed backbone. Colocation facility does bring certain expectation in terms of the small form factor and energy consumption of the platform.

 

Another key innovation in QFP3.0 is an integrated layer2 sub-system, it allows a single chip solution for 100G/40G/10G I/O integration including ingress classification and oversubscription buffering without the need for a feeder/consumer ASIC which were required in previous generation. It significantly brings down entire Catalyst 8500 Series Edge Platforms design into 1RU form factor to be well positioned for colocation and DC deployment.

 

The press release in 2008 was “The Cisco ASR 1000 Series is powered by the new Cisco QuantumFlow Processor (QFP), the industry's most advanced networking chipset.” Now in 2020 with another decade of continuous ASIC innovation to lead the enterprise WAN transformation by Cisco, I am excited to say that QFP3.0 is still the industry’s most advanced networking chipset.