Re: Slip errors increasing in E1 Contolller + Interface

bagvanliju · ‎12-12-2008

Hi,

I am facing Slip error in two contoller E1 ports.Service provider tested the link several times with error free...router vender came and tested every thing gave the update all are fine ...changed the E1 controller card and also the router ...no use

any body have any idea about the same ....would be very much helpfull ..this is an on going issue ....

below is the out put taken from router ...any inputs.even cisco tac told no issue with router ....i am running a multi link with 5 E1s ....

E1 0/3/1 is up.

Applique type is Channelized E1 - balanced

No alarms detected.

alarm-trigger is not set

Version info Firmware: 20071011, FPGA: 13, spm_count = 0

Framing is UNFRAMED, Line Code is HDB3, Clock Source is Line.

CRC Threshold is 320. Reported from firmware is 320.

Data in current interval (820 seconds elapsed):

0 Line Code Violations, 0 Path Code Violations

445 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins

445 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs

XXXXX#show controller

Interface GigabitEthernet0/0 (idb 0x66F90EDC)

Hardware is BCM1125 Internal MAC (Revision A3)

network link is up

Config is 100Mbps, Full Duplex

Selected media-type is RJ45

SFP is not present

MAC Registers:

E1 0/2/1 is up.

Applique type is Channelized E1 - balanced

No alarms detected.

alarm-trigger is not set

Version info Firmware: 20071011, FPGA: 13, spm_count = 0

Framing is UNFRAMED, Line Code is HDB3, Clock Source is Line.

CRC Threshold is 320. Reported from firmware is 320.

Data in current interval (820 seconds elapsed):

0 Line Code Violations, 0 Path Code Violations

215 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins

215 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs

XXXXX#s ver

Cisco IOS Software, 3800 Software (C3845-ADVIPSERVICESK9-M), Version 12.4(15)T4,

RELEASE SOFTWARE (fc2)

Technical Support: http://www.cisco.com/techsupport

Compiled Thu 13-Mar-08 09:02 by prod_rel_team

ROM: System Bootstrap, Version 12.4(13r)T, RELEASE SOFTWARE (fc1)

XXXX uptime is 20 weeks, 6 days, 3 hours, 11 minutes

System returned to ROM by power-on

System restarted at 03:15:09 UTC Sat Jul 19 2008

System image file is "flash:c3845-advipservicesk9-mz.124-15.T4.bin"

ujil

cfolkerts · ‎12-12-2008

I had a similar problem a while back. Here is the response that I reveived from Cisco TAC.

The second port on a 2 T1 VWIC will have to be set to clock source internal because the 2 port VWIC has a single common clocking chip in it. Two clock sources to each of the ports on the same VWIC will result in slips.

Set the second port to internal, on both vwics. This will fix it.

HTH

bagvanliju · ‎12-12-2008

Hai Clifton,

Thanks for the reply,This is a multilink with 5 E1 MPLS connnectivity.ISP had shared the Error report in PE router...no erros observed in their sonet (for 5 KLMs)...both end clock source is line.. SDH is generating the clock ...in this case any suggestion .so just one more confirmation can i change the clock source to internal for second port ???

kindly reply

ujil

viyuan700 · ‎12-12-2008

read Slip Secs Counter Increasing on the following link. Maybe can be helpful

http://www.cisco.com/en/US/tech/tk713/tk628/technologies_tech_note09186a00801095a3.shtml

cfolkerts · ‎12-15-2008

Yes, you can change the clock source to internal for the second port. The configuration is done under the controller config.

bagvanliju · ‎12-16-2008

Hi,

Thanks for the update ..still working on it ..will do the same and share the results ...

ujil