I would like to port channel 2x 3560x using maximim port members (8).
To cable this effeciently for max performance, I believe it would be wise to split them across the chasis ASICs.
Does anyone know how the ASICs are split.
I believe there are 3x ASICS
port 1-24 use ASIC1
port 25-48 use ASIC2
port 49 - 52 use ASIC0
Can anyone confirm / or know for sure ?
That's definitely how it is on the 3750X. I suspect 3560X is the same.
See this Cisco Live presentation (BRKARC-3437, slide 11)
Thanks for reponse.
Does anyone know the ASIC layout for the Cisco 4948's ?
I don't understand why this info is so sooo difficult to obtain. Surelly cisco should be boasting how great the hardware acrhitecture is (uhmmm)
But still can't work out how many ASICs on a 4948:
Interface Gigaport Phyport Aggport PimPhyport
Gi1/2 40 320 2 1
The port ASICs on the Catalyst 4948 are stub ASICs known as GrandPrix and there are six of them in the switch, each supporting 8-ports. The GrandPrix port ASICs are in turn connected to the K2 ASIC which is a centralised Packet Processing Engine (PPE) and Fast Forwarding Engine (FFE).
Each of the port ASICs provides wirespeed connectivity for the eight ports on it so I'm not sure if there's any performance gain to be had spreading a port-channel across different ASICs. That aside, here's how to find the information you're after on the Catalyst 4948.
The simplest way to find the port mapping is with the show platform chassis command. What I've noticed is a difference in the output depending upon IOS version. On late versions you get a nicely formated output where it's very simple to see port-to-ASIC mapping:
4948#show platform chassis
Spurious linecard interrupts : total=0, consecutive=0, max consecutive=0
Not handled linecard interrupts: total=0, consecutive=0, max consecutive=0
0 Grandprix 0 RJ-45 Gi1/2
0 Grandprix 1 RJ-45 Gi1/1
0 Grandprix 2 RJ-45 Gi1/4
0 Grandprix 3 RJ-45 Gi1/3
0 Grandprix 4 RJ-45 Gi1/6
0 Grandprix 5 RJ-45 Gi1/5
0 Grandprix 6 RJ-45 Gi1/8
0 Grandprix 7 RJ-45 Gi1/7
1 Grandprix 0 RJ-45 Gi1/10
1 Grandprix 1 RJ-45 Gi1/9
5 Grandprix 7 RJ-45 Gi1/47
5 Grandprix 7 No Gbic Gi1/47
If you happen to be running an earlier releasse, and I don't know when this changed, the output is a little less obvious so it's better to use the command show platform chassis | in GrandprixPort which outputs something along the lines of the following:
StubPortMan GrandprixPort 1/2:
GrandprixPortMan Grandprix 1-1() ( 0 ):
StubPortMan GrandprixPort 1/1:
GrandprixPortMan Grandprix 1-1() ( 1 ):
StubPortMan GrandprixPort 1/4:
GrandprixPortMan Grandprix 1-1() ( 2 ):
StubPortMan GrandprixPort 1/3:
GrandprixPortMan Grandprix 1-1() ( 3 ):
StubPortMan GrandprixPort 1/6:
GrandprixPortMan Grandprix 1-1() ( 4 ):
StubPortMan GrandprixPort 1/5:
GrandprixPortMan Grandprix 1-1() ( 5 ):
StubPortMan GrandprixPort 1/8:
GrandprixPortMan Grandprix 1-1() ( 6 ):
StubPortMan GrandprixPort 1/7:
GrandprixPortMan Grandprix 1-1() ( 7 ):
StubPortMan GrandprixPort 1/10:
GrandprixPortMan Grandprix 1-2() ( 0 ):
StubPortMan GrandprixPort 1/9:
GrandprixPortMan Grandprix 1-2() ( 1 ):
StubPortMan GrandprixPort 1/12:
GrandprixPortMan Grandprix 1-2() ( 2 ):
StubPortMan GrandprixPort 1/11:
While not obvious, the format of the output is Grandprix 1-X() ( Y ) where X is the ASIC and Y is the port of the ASIC.
Either way you have to go about it, the mapping of interface to ASIC is as follows:
Hope that helps.