MLS QoS on 3560 and 3750 - srr-queue bandwidth limit

[Difan Zhao]

Hi experts,

I feel that 3560 and 3750 perform differently with the following two commands:

srr-queue bandwidth shape 5 0 0 0

srr-queue bandwidth limit 50

On 3750, the bandwidth for queue 1 is limited to 100mbps x 50% / 5 = 10mbps

On 3560, the bandwidth for queue 1 is limited to the smaller value of BW / shape weight and BW x limit%.

Does it sound about right??

Another question, is there a way to check for mls qos input queue drops? The show mls qos interface xxx stat only shows the output queue drops. Maybe for some reason the input queue never drops??

Thanks!

[Axel Luttgens]

Hello Difan,

On 3750, the bandwidth for queue 1 is limited to 100mbps x 50% / 5 = 10mbps
On 3560, the bandwidth for queue 1 is limited to the smaller value of BW / shape weight and BW x limit%. 
Does it sound about right??

I don't know... :-(

Another question, is there a way to check for mls qos input queue drops? The show mls qos interface xxx stat only shows the output queue drops. Maybe for some reason the input queue never drops??

The "sh plat port-asic stat" command should provide you with some info about those drops.

There seems to be some kind of consensus about the fact that ingress drops reveal deeper problems, such as stacking congestion (in the case of stacked switches).

Now, more prosaically, it is only recently that the "sh mls qos int stat" command displays output drops...

HTH,

Axel

[ralphcarter]

Also, are you connecting the same ports? Remember that there are shared buffers for the ASIC. The ASIC controls a group of ports and there is a common pool of buffers that is used for these ports.

Test it using same port connections. For example, connect device to port G1/0/1 and leave g1/0/2 - 4 empty on both switches.

[Difan Zhao]

That's interesting to know. Nope I didn't know about this shared buffer thing until I read your post and did some research. I will try that. Is there a place to find out what ports are controlled by one ASIC? Are the uplink ports 25~28 on separate ASIC since they are uplinks?

[Axel Luttgens]

Is there a place to find out what ports are controlled by one ASIC?

You may try "show platform pm if-numbers" and have a look at the "port" column (asic/port).

HTH,

Axel

[Difan Zhao]

Hi Axel, the command is cool. It shows that one ASIC is controlling four ports. Is the ASIC controlling the uplink ports (g1/0/25~28) same as the ASIC controller for the rest ports? I was assuming that the uplink ports is each controlled by one ASIC. If they are all the same ASIC, there is really no difference which port to use as the uplink port, correct?

Thanks!

[Axel Luttgens]

Hello Difan,

Sorry to be a bit late at replying, just too much to do those times.

It's difficult to tell, since this would require to have a description of the chips (a data sheet); Cisco is quite secretive for those matters, and the only way is to try to find some info on the net...

For example, a 2960-24TC seems to rely on a Sasquatch-CR asic, devised for a "24+2" ports design; one may guess that even if there is a single chip, the 2 uplink ports (Gb/s) must somehow be handled differently than the other 24 ports (10/100 Mb/s).

As far as the 3560 and 3750 are concerned, one may find some info in the "Catalyst 3750 & 3560 Architecture" document at Cisco live! (ref. BRKARC-3437).

HTH,

Axel