Cisco C1117

[alpha76]

Hi,

We have a Cisco C1117-4P connected to a vdsl line. However, it has recently stopped being able to connect to the carrier. It worked for over one year and then just stopped. I have tested the line with other routers, and it works fine, so I know everything is fine with the login details and circuit.

sh controllers vdSL 0/2/0
Controller VDSL 0/2/0 is DOWN

Daemon Status: TRAINING

XTU-R (DS) XTU-C (US)
Chip Vendor ID: ' ' ' '
Chip Vendor Specific: 0x0000 0x0000
Chip Vendor Country: 0x0000 0x0000
Modem Vendor ID: ' ' ' '
Modem Vendor Specific: 0x0000 0x0000
Modem Vendor Country: 0x0000 0x0000
Serial Number Near:
Serial Number Far:
Modem Version Near:
Modem Version Far:

Modem Status: Line NOT intialized
DSL Config Mode: AUTO
Trained Mode:

TC Mode: UNKNOWN
Selftest Result: 0x00
DELT configuration: disabled
DELT state: not running

Failed full inits: 0
Short inits: 0
Failed short inits: 0

Modem FW Version:
Modem PHY Version:
Modem PHY Source: System

Training Log : Stopped
Training Log Filename: flash:vdsllog.bin

I need some help with the problem and how to fix it. Can anyone please assist?

[M02@rt37]

Hello @alpha76,

Do you double-check the VDSL settings such as encapsulation, DSL profile, and any specific configuration parameters required by your carrier?

Do you try a simple shut/no shut of the interfave VDSL 0/2/0?

Could you please provide debug output?  #debug vdsl events - #debug ppp negociation

[alpha76]

Hi M02@rt37 

The VDSL controller has been set to auto. It has always been set like that. The interface configuration has stayed the same, and I have compared it to other customers. It looks fine. On the front of the router, the vdsl interface repeatedly flashes green however, it was solid before it stopped working.

Here is a debug of the vdsl. 

Router#debug vdsl all.
VDSL daemon error condition debugging is on
VDSL daemon state machine debugging is on
VDSL daemon information debugging is on
VDSL ipc error condition debugging is on
VDSL ipc tx debugging is on
VDSL IPC rx debugging is on
VDSL MIB error debugging is on
VDSL MIB information debugging is on
Router#
*Jun 15 21:23:51.356: VDSL 0/2/0: line_state_notif on slot 0, subslot 2 port 128

*Jun 15 21:23:52.485: VDSL 0/2/0: line_state_notif on slot 0, subslot 2 port 128

*Jun 15 21:23:53.589: VDSL 0/2/0: line_state_notif on slot 0, subslot 2 port 128

*Jun 15 21:23:55.712: VDSL 0/2/0: line_state_notif on slot 0, subslot 2 port 128

*Jun 15 21:23:56.840: VDSL 0/2/0: line_state_notif on slot 0, subslot 2 port 128

*Jun 15 21:23:57.310: VDSL 0/2/0: Updating 16-bit GAIN, dir[2]
*Jun 15 21:23:57.310: VDSL 0/2/0: [0x7F44A1A03C] Update expecting block to 1.
*Jun 15 21:23:57.311: VDSL 0/2/0: [0x7F44A1A03C] update expecting block to 1.
*Jun 15 21:23:57.311: VDSL 0/2/0: [0x7F44A1A03C] Last block [0]
*Jun 15 21:23:57.311: VDSL 0/2/0: [0x7F44A1A03C] report completed seq [131], validate buf [0]
*Jun 15 21:23:59.960: VDSL 0/2/0: line_state_notif on slot 0, subslot 2 port 128

*Jun 15 21:24:01.077: VDSL 0/2/0: line_state_notif on slot 0, subslot 2 port 128

*Jun 15 21:24:01.988: VDSL 0/2/0: Updating LINE ST line[0]
*Jun 15 21:24:01.989: VDSL 0/2/0: pm_linesec_counter update type[0] endpt[1] interval[0]
*Jun 15 21:24:01.989: VDSL 0/2/0: pm_linesec_counter update type[0] endpt[2] interval[0]
*Jun 15 21:24:01.989: VDSL 0/2/0: pm_linesec_counter update type[1] endpt[1] interval[0]
*Jun 15 21:24:01.989: VDSL 0/2/0: pm_linesec_counter update type[1] endpt[2] interval[0]
*Jun 15 21:24:01.990: VDSL 0/2/0: pm_linesec_counter update type[3] endpt[1] interval[0]
*Jun 15 21:24:02.001: VDSL 0/2/0: pm_linesec_counter update type[3] endpt[2] interval[0]
*Jun 15 21:24:02.001: VDSL 0/2/0: Updating 8-bit BIT ALLOC, dir[2]
*Jun 15 21:24:02.001: VDSL 0/2/0: [0x7F44A8A2D0] Updating current_report_seq [4294967295]->[142]
*Jun 15 21:24:02.001: VDSL 0/2/0: [0x7F44A8A2D0] Update expecting block to 1.
*Jun 15 21:24:02.001: VDSL 0/2/0: [0x7F44A8A2D0] update expecting block to 1.
*Jun 15 21:24:02.002: VDSL 0/2/0: [0x7F44A8A2D0] Last block [0]
*Jun 15 21:24:02.002: VDSL 0/2/0: [0x7F44A8A2D0] report completed seq [142], validate buf [1]
*Jun 15 21:24:06.490: VDSL 0/2/0: pm_linesec_counter update type[4] endpt[1] interval[0]
*Jun 15 21:24:06.490: VDSL 0/2/0: pm_linesec_counter update type[4] endpt[2] interval[0]
*Jun 15 21:24:06.491: VDSL 0/2/0: pm_linesec_counter update type[2] endpt[1] interval[0]
*Jun 15 21:24:06.491: VDSL 0/2/0: pm_linesec_counter update type[2] endpt[2] interval[0]
*Jun 15 21:24:06.491: VDSL 0/2/0: pm_lineinit_counter update type[0] interval[0]
*Jun 15 21:24:06.492: VDSL 0/2/0: pm_lineinit_counter update type[0] interval[0]
*Jun 15 21:24:06.492: VDSL 0/2/0: pm_lineinit_counter update type[1] interval[0]
*Jun 15 21:24:06.500: VDSL 0/2/0: pm_lineinit_counter update type[1] interval[0]
*Jun 15 21:24:06.501: VDSL 0/2/0: pm_lineinit_counter update type[2] interval[0]
*Jun 15 21:24:06.501: VDSL 0/2/0: pm_lineinit_counter update type[2] interval[0]
*Jun 15 21:24:10.990: VDSL 0/2/0: pm_channel_counter update type[0] channell[0] endpt[1] interval[0]
*Jun 15 21:24:10.990: VDSL 0/2/0: pm_channel_counter update type[1] channell[0] endpt[1] interval[0]
*Jun 15 21:24:10.991: VDSL 0/2/0: pm_channel_counter update type[3] channell[0] endpt[1] interval[0]
*Jun 15 21:24:10.991: VDSL 0/2/0: pm_channel_counter update type[4] channell[0] endpt[1] interval[0]
*Jun 15 21:24:10.991: VDSL 0/2/0: pm_channel_counter update type[2] channell[0] endpt[1] interval[0]
*Jun 15 21:24:11.204: VDSL 0/2/0: line_state_notif on slot 0, subslot 2 port 128

*Jun 15 21:24:13.316: VDSL 0/2/0: line_state_notif on slot 0, subslot 2 port 128

*Jun 15 21:24:15.440: VDSL 0/2/0: line_state_notif on slot 0, subslot 2 port 128

*Jun 15 21:24:15.620: VDSL 0/2/0: pm_datapath_counter update type[0] channell[0] endpt[0] interval[0]
*Jun 15 21:24:15.621: VDSL 0/2/0: pm_datapath_counter update type[1] channell[0] endpt[0] interval[0]
*Jun 15 21:24:15.621: VDSL 0/2/0: pm_datapath_counter update type[2] channell[0] endpt[1] interval[0]
*Jun 15 21:24:15.621: VDSL 0/2/0: pm_datapath_counter update type[2] channell[0] endpt[2] interval[0]
*Jun 15 21:24:16.569: VDSL 0/2/0: line_state_notif on slot 0, subslot 2 port 128

*Jun 15 21:24:24.692: VDSL 0/2/0: Updating 16-bit DELT_HLOG, dir[2]
*Jun 15 21:24:24.692: VDSL 0/2/0: [0x7F449B9E2C] Update expecting block to 1.
*Jun 15 21:24:24.692: VDSL 0/2/0: [0x7F449B9E2C] update expecting block to 1.
*Jun 15 21:24:24.692: VDSL 0/2/0: [0x7F449B9E2C] Last block [0]
*Jun 15 21:24:24.693: VDSL 0/2/0: [0x7F449B9E2C] report completed seq [181], validate buf [1]
*Jun 15 21:24:29.192: VDSL 0/2/0: Updating 16-bit DELT_SNR_TONE, dir[2]
*Jun 15 21:24:29.192: VDSL 0/2/0: [0x7F44A621C8] Update expecting block to 1.
*Jun 15 21:24:29.192: VDSL 0/2/0: [0x7F44A621C8] update expecting block to 1.
*Jun 15 21:24:29.192: VDSL 0/2/0: [0x7F44A621C8] Last block [0]
*Jun 15 21:24:29.192: VDSL 0/2/0: [0x7F44A621C8] report completed seq [182], validate buf [1]
*Jun 15 21:24:29.193: VDSL 0/2/0: Updating 16-bit DELT_SNR_TONE, dir[1]
*Jun 15 21:24:29.193: VDSL 0/2/0: [0x7F44A5A19C] Update expecting block to 1.
*Jun 15 21:24:29.193: VDSL 0/2/0: [0x7F44A5A19C] update expecting block to 1.
*Jun 15 21:24:29.193: VDSL 0/2/0: [0x7F44A5A19C] Last block [0]
*Jun 15 21:24:29.193: VDSL 0/2/0: [0x7F44A5A19C] report completed seq [183], validate buf [1]
*Jun 15 21:24:33.693: VDSL 0/2/0: Updating complex DELT_HLIN, dir[2]
*Jun 15 21:24:33.693: VDSL 0/2/0: [0x7F44ABA3D8] Update expecting block to 1.
*Jun 15 21:24:33.693: VDSL 0/2/0: [0x7F44ABA3D8] update expecting block to 1.
*Jun 15 21:24:33.694: VDSL 0/2/0: Updating complex DELT_HLIN, dir[2]
*Jun 15 21:24:33.694: VDSL 0/2/0: [0x7F44ABA3D8] Update expecting block to 2.
*Jun 15 21:24:33.694: VDSL 0/2/0: [0x7F44ABA3D8] update expecting block to 2.
*Jun 15 21:24:33.694: VDSL 0/2/0: [0x7F44ABA3D8] Last block [1]
*Jun 15 21:24:33.694: VDSL 0/2/0: [0x7F44ABA3D8] report completed seq [184], validate buf [0]
*Jun 15 21:24:38.192: VDSL 0/2/0: Updating 16-bit DELT_QLN, dir[2]
*Jun 15 21:24:38.192: VDSL 0/2/0: [0x7F449D1EB0] Update expecting block to 1.
*Jun 15 21:24:38.192: VDSL 0/2/0: [0x7F449D1EB0] update expecting block to 1.
*Jun 15 21:24:38.192: VDSL 0/2/0: [0x7F449D1EB0] Last block [0]
*Jun 15 21:24:38.192: VDSL 0/2/0: [0x7F449D1EB0] report completed seq [187], validate buf [1]
*Jun 15 21:24:42.692: VDSL 0/2/0: Updating 16-bit DELT_HLOG_TONE, dir[2]
*Jun 15 21:24:42.692: VDSL 0/2/0: [0x7F44A320C0] Update expecting block to 1.
*Jun 15 21:24:42.692: VDSL 0/2/0: [0x7F44A320C0] update expecting block to 1.
*Jun 15 21:24:42.692: VDSL 0/2/0: [0x7F44A320C0] Last block [0]
*Jun 15 21:24:42.692: VDSL 0/2/0: [0x7F44A320C0] report completed seq [189], validate buf [1]
*Jun 15 21:24:47.193: VDSL 0/2/0: Updating complex DELT_HLIN_TONE, dir[2]
*Jun 15 21:24:47.193: VDSL 0/2/0: [0x7F44AEA45C] Update expecting block to 1.
*Jun 15 21:24:47.193: VDSL 0/2/0: [0x7F44AEA45C] update expecting block to 1.
*Jun 15 21:24:47.194: VDSL 0/2/0: Updating complex DELT_HLIN_TONE, dir[2]
*Jun 15 21:24:47.194: VDSL 0/2/0: [0x7F44AEA45C] Update expecting block to 2.
*Jun 15 21:24:47.194: VDSL 0/2/0: [0x7F44AEA45C] update expecting block to 2.
*Jun 15 21:24:47.194: VDSL 0/2/0: [0x7F44AEA45C] Last block [1]
*Jun 15 21:24:47.194: VDSL 0/2/0: [0x7F44AEA45C] report completed seq [190], validate buf [1]
*Jun 15 21:24:51.691: VDSL 0/2/0: Updating 16-bit DELT_QLN_TONE, dir[2]
*Jun 15 21:24:51.692: VDSL 0/2/0: [0x7F44A4A144] Update expecting block to 1.
*Jun 15 21:24:51.692: VDSL 0/2/0: [0x7F44A4A144] update expecting block to 1.
*Jun 15 21:24:51.692: VDSL 0/2/0: [0x7F44A4A144] Last block [0]
*Jun 15 21:24:51.692: VDSL 0/2/0: [0x7F44A4A144] report completed seq [191], validate buf [1]
*Jun 15 21:24:51.692: VDSL 0/2/0: Updating 16-bit DELT_QLN_TONE, dir[1]
*Jun 15 21:24:51.692: VDSL 0/2/0: [0x7F44A42118] Update expecting block to 1.
*Jun 15 21:24:51.692: VDSL 0/2/0: [0x7F44A42118] update expecting block to 1.
*Jun 15 21:24:51.692: VDSL 0/2/0: [0x7F44A42118] Last block [0]
*Jun 15 21:24:51.692: VDSL 0/2/0: [0x7F44A42118] report completed seq [192], validate buf [1]
*Jun 15 21:24:52.700: VDSL 0/2/0: line_state_notif on slot 0, subslot 2 port 128

*Jun 15 21:24:53.817: VDSL 0/2/0: line_state_notif on slot 0, subslot 2 port 128

*Jun 15 21:24:55.941: VDSL 0/2/0: line_state_notif on slot 0, subslot 2 port 128

*Jun 15 21:24:57.060: VDSL 0/2/0: line_state_notif on slot 0, subslot 2 port 128

*Jun 15 21:25:00.882: VDSL 0/2/0: Updating 16-bit GAIN, dir[2]
*Jun 15 21:25:00.882: VDSL 0/2/0: [0x7F44A1A03C] Update expecting block to 1.
*Jun 15 21:25:00.882: VDSL 0/2/0: [0x7F44A1A03C] update expecting block to 1.
*Jun 15 21:25:00.882: VDSL 0/2/0: [0x7F44A1A03C] Last block [0]
*Jun 15 21:25:00.882: VDSL 0/2/0: [0x7F44A1A03C] report completed seq [198], validate buf [1]
*Jun 15 21:25:04.184: VDSL 0/2/0: line_state_notif on slot 0, subslot 2 port 128

*Jun 15 21:25:05.299: VDSL 0/2/0: line_state_notif on slot 0, subslot 2 port 128

*Jun 15 21:25:05.481: VDSL 0/2/0: Updating LINE ST line[0]
*Jun 15 21:25:05.481: VDSL 0/2/0: pm_linesec_counter update type[0] endpt[1] interval[0]
*Jun 15 21:25:05.482: VDSL 0/2/0: pm_linesec_counter update type[0] endpt[2] interval[0]
*Jun 15 21:25:05.482: VDSL 0/2/0: pm_linesec_counter update type[1] endpt[1] interval[0]
*Jun 15 21:25:05.482: VDSL 0/2/0: pm_linesec_counter update type[1] endpt[2] interval[0]
*Jun 15 21:25:05.483: VDSL 0/2/0: pm_linesec_counter update type[3] endpt[1] interval[0]
*Jun 15 21:25:05.493: VDSL 0/2/0: pm_linesec_counter update type[3] endpt[2] interval[0]
*Jun 15 21:25:05.493: VDSL 0/2/0: Updating 8-bit BIT ALLOC, dir[2]
*Jun 15 21:25:05.494: VDSL 0/2/0: [0x7F44A8A2D0] Updating current_report_seq [4294967295]->[209]
*Jun 15 21:25:05.494: VDSL 0/2/0: [0x7F44A8A2D0] Update expecting block to 1.
*Jun 15 21:25:05.494: VDSL 0/2/0: [0x7F44A8A2D0] update expecting block to 1.
*Jun 15 21:25:05.494: VDSL 0/2/0: [0x7F44A8A2D0] Last block [0]
*Jun 15 21:25:05.494: VDSL 0/2/0: [0x7F44A8A2D0] report completed seq [209], validate buf [0]
*Jun 15 21:25:06.428: VDSL 0/2/0: line_state_notif on slot 0, subslot 2 port 128

*Jun 15 21:25:07.546: VDSL 0/2/0: line_state_notif on slot 0, subslot 2 port 128

*Jun 15 21:25:10.072: VDSL 0/2/0: pm_linesec_counter update type[4] endpt[1] interval[0]
*Jun 15 21:25:10.072: VDSL 0/2/0: pm_linesec_counter update type[4] endpt[2] interval[0]
*Jun 15 21:25:10.074: VDSL 0/2/0: pm_linesec_counter update type[2] endpt[1] interval[0]
*Jun 15 21:25:10.074: VDSL 0/2/0: pm_linesec_counter update type[2] endpt[2] interval[0]
*Jun 15 21:25:10.074: VDSL 0/2/0: pm_lineinit_counter update type[0] interval[0]
*Jun 15 21:25:10.076: VDSL 0/2/0: pm_lineinit_counter update type[0] interval[0]
*Jun 15 21:25:10.076: VDSL 0/2/0: pm_lineinit_counter update type[1] interval[0]
*Jun 15 21:25:10.084: VDSL 0/2/0: pm_lineinit_counter update type[1] interval[0]
*Jun 15 21:25:10.085: VDSL 0/2/0: pm_lineinit_counter update type[2] interval[0]
*Jun 15 21:25:10.085: VDSL 0/2/0: pm_lineinit_counter update type[2] interval[0]
*Jun 15 21:25:11.674: VDSL 0/2/0: line_state_notif on slot 0, subslot 2 port 128

*Jun 15 21:25:12.786: VDSL 0/2/0: line_state_notif on slot 0, subslot 2 port 128

*Jun 15 21:25:14.694: VDSL 0/2/0: pm_channel_counter update type[0] channell[0] endpt[1] interval[0]
*Jun 15 21:25:14.694: VDSL 0/2/0: pm_channel_counter update type[1] channell[0] endpt[1] interval[0]
*Jun 15 21:25:14.694: VDSL 0/2/0: pm_channel_counter update type[3] channell[0] endpt[1] interval[0]
*Jun 15 21:25:14.695: VDSL 0/2/0: pm_channel_counter update type[4] channell[0] endpt[1] interval[0]
*Jun 15 21:25:14.695: VDSL 0/2/0: pm_channel_counter update type[2] channell[0] endpt[1] interval[0]
*Jun 15 21:25:14.910: VDSL 0/2/0: line_state_notif on slot 0, subslot 2 port 128

*Jun 15 21:25:16.024: VDSL 0/2/0: line_state_notif on slot 0, subslot 2 port 128

*Jun 15 21:25:17.153: VDSL 0/2/0: line_state_notif on slot 0, subslot 2 port 128

*Jun 15 21:25:18.269: VDSL 0/2/0: line_state_notif on slot 0, subslot 2 port 128

*Jun 15 21:25:19.384: VDSL 0/2/0: pm_datapath_counter update type[0] channell[0] endpt[0] interval[0]
*Jun 15 21:25:19.384: VDSL 0/2/0: pm_datapath_counter update type[1] channell[0] endpt[0] interval[0]
*Jun 15 21:25:19.385: VDSL 0/2/0: pm_datapath_counter update type[2] channell[0] endpt[1] interval[0]
*Jun 15 21:25:19.386: VDSL 0/2/0: pm_datapath_counter update type[2] channell[0] endpt[2] interval[0]
*Jun 15 21:25:28.384: VDSL 0/2/0: Updating 16-bit DELT_HLOG, dir[2]
*Jun 15 21:25:28.384: VDSL 0/2/0: [0x7F449B9E2C] Update expecting block to 1.
*Jun 15 21:25:28.384: VDSL 0/2/0: [0x7F449B9E2C] update expecting block to 1.
*Jun 15 21:25:28.385: VDSL 0/2/0: [0x7F449B9E2C] Last block [0]
*Jun 15 21:25:28.385: VDSL 0/2/0: [0x7F449B9E2C] report completed seq [252], validate buf [0]
*Jun 15 21:25:31.396: VDSL 0/2/0: line_state_notif on slot 0, subslot 2 port 128

*Jun 15 21:25:32.512: VDSL 0/2/0: line_state_notif on slot 0, subslot 2 port 128

*Jun 15 21:25:32.991: VDSL 0/2/0: Updating 16-bit DELT_SNR_TONE, dir[2]
*Jun 15 21:25:32.991: VDSL 0/2/0: [0x7F44A621C8] Update expecting block to 1.
*Jun 15 21:25:32.991: VDSL 0/2/0: [0x7F44A621C8] update expecting block to 1.
*Jun 15 21:25:32.992: VDSL 0/2/0: [0x7F44A621C8] Last block [0]
*Jun 15 21:25:32.992: VDSL 0/2/0: [0x7F44A621C8] report completed seq [255], validate buf [0]
*Jun 15 21:25:32.992: VDSL 0/2/0: Updating 16-bit DELT_SNR_TONE, dir[1]
*Jun 15 21:25:32.992: VDSL 0/2/0: [0x7F44A5A19C] Update expecting block to 1.
*Jun 15 21:25:32.992: VDSL 0/2/0: [0x7F44A5A19C] update expecting block to 1.
*Jun 15 21:25:32.992: VDSL 0/2/0: [0x7F44A5A19C] Last block [0]
*Jun 15 21:25:32.992: VDSL 0/2/0: [0x7F44A5A19C] report completed seq [256], validate buf [0]
*Jun 15 21:25:37.492: VDSL 0/2/0: Updating complex DELT_HLIN, dir[2]
*Jun 15 21:25:37.492: VDSL 0/2/0: [0x7F44ABA3D8] Update expecting block to 1.
*Jun 15 21:25:37.493: VDSL 0/2/0: [0x7F44ABA3D8] update expecting block to 1.
*Jun 15 21:25:37.493: VDSL 0/2/0: Updating complex DELT_HLIN, dir[2]
*Jun 15 21:25:37.493: VDSL 0/2/0: [0x7F44ABA3D8] Update expecting block to 2.
*Jun 15 21:25:37.493: VDSL 0/2/0: [0x7F44ABA3D8] update expecting block to 2.
*Jun 15 21:25:37.493: VDSL 0/2/0: [0x7F44ABA3D8] Last block [1]
*Jun 15 21:25:37.493: VDSL 0/2/0: [0x7F44ABA3D8] report completed seq [257], validate buf [1]
*Jun 15 21:25:41.991: VDSL 0/2/0: Updating 16-bit DELT_QLN, dir[2]
*Jun 15 21:25:41.991: VDSL 0/2/0: [0x7F449D1EB0] Update expecting block to 1.
*Jun 15 21:25:41.991: VDSL 0/2/0: [0x7F449D1EB0] update expecting block to 1.
*Jun 15 21:25:41.992: VDSL 0/2/0: [0x7F449D1EB0] Last block [0]
*Jun 15 21:25:41.992: VDSL 0/2/0: [0x7F449D1EB0] report completed seq [260], validate buf [0]
*Jun 15 21:25:46.493: VDSL 0/2/0: Updating 16-bit DELT_HLOG_TONE, dir[2]
*Jun 15 21:25:46.493: VDSL 0/2/0: [0x7F44A320C0] Update expecting block to 1.
*Jun 15 21:25:46.493: VDSL 0/2/0: [0x7F44A320C0] update expecting block to 1.
*Jun 15 21:25:46.493: VDSL 0/2/0: [0x7F44A320C0] Last block [0]
*Jun 15 21:25:46.494: VDSL 0/2/0: [0x7F44A320C0] report completed seq [262], validate buf [0]un all
VDSL daemon error condition debugging is off
VDSL daemon state machine debugging is off
VDSL daemon information debugging is off
VDSL ipc error condition debugging is off
VDSL ipc tx debugging is off
VDSL ipc rx debugging is off
VDSL MIB error debugging is off
VDSL MIB information debugging is off
All possible debugging has been turned off

---