3850 Switch Port-to-ASIC Mapping

[Nickolus Looper]

Hello -

Does anyone know how to find out the port-to-ASIC mapping on the 3850X series switches?

On some platforms, 'show interface capabilities' yields this info...on others, 'show platform pm if-numbers' can give a clue.

I'm having no luck figuring this out on the 3850X though.

Thanks!

Nick

[Mark Malone · Accepted solution]

Hi

Its different archioctecture on ios-xe 38s and 36s ,They haved a 1 UDAP ASIC for 24 ports 2 UDAP ASICs for 48 port model not like the 37s where its mapped to each port

explains it further in this but i have seen the best documents on the Cisco live website if you search 3850 Archictecture

https://www.cisco.com/c/en/us/products/collateral/switches/catalyst-3850-series-switches/white-paper-c11-734429.html

It is powered by the new UADP ASIC. UADP stands for Unified Access Data Plane. What is unified is that in addition to a shared memory switch function, the silicon runs the CAPWAP protocol in hardware to give really fast WiFi performance. Three of the UADP ASICs are used in the 5760 Wireless Lan Controller to provide 60 Gb/s of WiFi capacity. In the 3850 switches, an ASIC is used to host 24 ports. A 48 port switch has two UADP ASICs. The same ASIC runs the 3650, a version without the stacking capability.

[Nickolus Looper]

Thanks so much for the informative info - this really spells it all out!

[5dng]

I found this command appears to show the asic # on a C3850XS-48. They are assigned in groups of 4 ports.

Switch#sh pl so fed sw 1 qos qsb interface tenGigabitEthernet 1/0/1
QoS subblock information:
  Name:TenGigabitEthernet1/0/1 iif_id:0x00000000000008 iif_type:ETHER(146)
  qsb ptr:0xffb8a848b8
  Port type = Wired port
  asic_num:7 is_uplink:false init_done:1
  FRU events: Active-0, Inactive-0
  def_qos_label:0 def_le_priority:13
  trust_enabled:true trust_type:TRUST_DSCP ifm_trust_type:0
  LE priority:13 LE tablemap handle(in, out): (0,0)
  Stats (plc,q) export counters (in/out): 0/0
  Policy Info:
    Ingress Policy:nil
    Egress Policy:nil
    TCG(in,out):((nil), (nil))
  Policer Info: Aggregate
    Ingress policer block: Not allocated
    Egress policer block: Not allocated
    Instance Handle: Not allocated
  Policer Info: Microflow
    Ingress policer block: Not allocated
    Egress policer block: Not allocated
    Instance Handle: Not allocated
  Queueing Info:
    def_queuing = 1, shape_rate:0 interface_rate_kbps:10000000
    Port shaper:false
    lbl_to_qmap_index:0