The Cisco® Catalyst® 9500 Series switch is Cisco’s lead fixed enterprise core switching platform and is part of the Catalyst 9000 family. The Cisco Catalyst 9500 high performance series was introduced in mid-2019 to provide a migration path for Catalyst 6500/6800 (non-XL) series platforms by delivering Core scale (MAC, route, and Access Control List [ACL]) and hardware performance also providing high-availability capabilities such as StackWise Virtual, Patching, Graceful Insertion and Removal (GIR), Cisco Nonstop Forwarding with Stateful Switchover (NSF/SSO), redundant platinum-rated power supplies, and fans.
The Catalyst 9500 Series continues to shape the future with continued innovation to help re-imagine connections, reinforce security and redefine the experience for Enterprise Campus Core and Edge. The new C9500X-28C8D switch is the industry’s first purpose-built 400, 200^, 100, 50*, 40^, * and 10* Gigabit Ethernet switch. The design of the switch helps it address the Enterprise Campus and Edge requirements.
The Catalyst 9500X switch delivers (MAC addresses, IP unicast & multicast routes, MPLS labels) and deep buffering for enterprise applications. The Catalyst 9500X switch includes 28 non-blocking 100 Gigabit Ethernet Quad Small Form-Factor Pluggable (QSFP28) and 8 non-blocking 400 Gigabit Ethernet Quad Small Form-Factor Pluggable Double Density (QSFP-DD) ports to provide a migration path for Cisco Catalyst 6500/6880 XL platforms.
The X-Factor – Cisco Catalyst 9500X-28C8D:
The new Cisco Silicon One Q200 ASIC powers the Cisco Catalyst 9500X-28C8D which can provide a total switching capacity of 12.8 Tbps. The ASIC is fabricated using 7nm technology which enables very high performance at a low power footprint. This single Cisco Silicon One Q200 ASIC provides ~6 times the performance provided by the UADP 3.0 ASIC. This unlocks higher non-blocking port speeds and densities while also boasting a 2.5X increase in buffers. The Virtual Output Queue (VoQ) forwarding model also eliminates Head of Line (HoL) blocking commonly seen in very high-speed circuits.
Highlights of the Catalyst 9500X-28C8D include:
Intel® 2.43-GHz x86 CPU with 8 cores and 32-GB of DDR4 memory allowing for application hosting.
80MB of dedicated buffer to allow for low latency packet forwarding.
8GB of on-demand High Bandwidth Memory (HBM) providing very deep packet buffers and route table expansion.
Up to 960 GB of SSD local storage for container-based application hosting (2x 10G KR ports)
ASIC tables for switching scale up to 256K MAC addresses and routing scale up to 2M routes.
Customizable SDM templates allowing for tweaking already high scale numbers even further.
Hardware support for line-rate 256-bit 802.1ae MACsec and WAN-MACsec data encryption.
Hardware support for Precision Time Protocol (PTP, IEEE 1588v2) with accurate clock synchronization and sub-microsecond accuracy, suitable for distribution and synchronization of time and frequency.
Reversible Airflow – A first for Catalyst 9000 switches
Accounting for different installation requirements, the Catalyst 9500X-28C8D is the first Catalyst 9000 series switch to provide two different directions for airflow – Back to front (port side exhaust) or front to back (port side intake) Two different fan tray units are available for order as per requirements. Enhancements to the design allows the same power supply to be used for both directions. The power supply fans switch the direction of airflow depending on the direction of the fan inserted.
Deep Buffers and VoQ Architecture – Optimized for Edge Deployments:
The new Catalyst 9500X-28C8D is built on a multi slice-based ASIC design with a Virtual Output Queue (VoQ) forwarding architecture. This design allows Network Processing Units (NPU) to operate independently in "Slices" with cross-communication over a crossbar "Fabric". This evolves the multi-core ASIC design used in UADP 2 and UADP 3.0 based Catalyst 9500 series switches.
To address the unique queuing challenges of campus edge devices, the design uses a forwarding architecture that uses a credit-based system for forwarding traffic by building Virtual queues between each ingress and egress interfaces independently. This design eliminates Head of Line (HoL) blocking which is illustrated in the figures below.
To also address the speed differences typically seen in Internet Edge devices, the Catalyst 9500X-28C8D boasts of impressively deep buffers. The switch has 80 MB dedicated buffers which enables low latency queueing for priority packets. The switch also has an additional 8 GB of on-demand High Bandwidth Memory (HBM) buffers which can be accessed to queue packets in case of speed mismatches between ingress and egress or to support micro-burst sensitive flows.
C9500X for continued Enterprise Core Leadership:
Catalyst 9500 family of switches are continuing the leadership in fixed Core/Distribution campus switches by providing full suite of Core features along with higher performance & scale. Moreover, C9500 series platform provides variety of port density for Enterprise campus core requirements.
Catalyst 9500 High Performance series switches provide best in class Core features set with unmatched Hardware performance scale for Catalyst 6500/6800 series non-XL deployments. It can be ideal for Campus Core, Collapsed Core + Distribution deployments.
The Catalyst 9500X-28C8D offers higher port speeds (Up to 8 ports of 400G) and superior Hardware performance scales (Up to 2M IPv4 routes, 256K MAC, and large buffer support) for migration of Catalyst 6500/6800 series XL deployments. With optimized performance and newly added IOS-XE features (such as WAN MACsec, Scaled MPLS, /SGACL), Catalyst 9500X-28C8D is ideal for Campus Core and Edge deployments. The higher scales also make it the prime upgrade option for Catalyst 6880/6500 XL deployments.
The Catalyst 9500X switch is not meant to replace the Catalyst 9500 high performance series of . Instead, the Silicon One based Catalyst 9500X switch complements the UADP 3.0 based Catalyst 9500 high performance series switches to build a robust and feature rich family of switches. Both switch series can continue to be positioned as required based on network design.
Dear all, May I know if the "system mtu jumbo" command will appear in the "show running-config" of a CGS2520 switch please? Or it will be hidden from the IOS config files? Thanks for your attention in advance!
I have a simple scenario as in the diagram:I am advertising a route 220.127.116.11/24 from R4 to AS 100. When I verify BGP table in the R1,R2,R3:R1#show ip bgpBGP table version is 8, local router ID is 18.104.22.168Network Next Hop Metric LocPrf Weight Path* i...
Thought just occured to me as to whether or not I should be able to ping acorss this trunk portswhile doing this lab In doing a HSRP lab between the switches I recognized there needed to be communication between the switches to elect the active...
Hi All I have 2 x Cisco 1140 Fws running in ASA mode. Active/Standby 2 x 9300s with a trunk between ten Cisco have depreciated the Redundant interface on the 1140s I have configured sub interfaces on one of the ports of FWs with ...
Can I point all switches to one querier in the l2 multicast network? Attached is the sample topology with each device config pointing to one switch NXOS1, which is the querier, or other devices will discover the querier NSOX1 vi...