Slip secs and erroed secs counter increasing in E1 link

[janith]

Hello

I have a E1 ATM link to my HUB router and am experiencing incrementing slip secns errors and errored secs. Telco looped the line with an ATM trafffic generator and found that these errors were not present then. Only when i connnect my 2611 to the E1 do i see the errors increasing. I know this is cos of a clocking misconfiguration but what should i do to rectify it. Already the clock sourse is LINE.

E1 0/0 is up.

Applique type is Channelized E1 - balanced

No alarms detected.

alarm-trigger is not set

Version info Firmware: 20040408, FPGA: 11

Framing is CRC4, Line Code is HDB3, Clock Source is Line.

CRC Threshold is 320. Reported from firmware is 0.

Data in current interval (55 seconds elapsed):

0 Line Code Violations, 0 Path Code Violations

2 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins

2 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs

Total Data (last 24 hours)

1467 Line Code Violations, 896 Path Code Violations,

3140 Slip Secs, 0 Fr Loss Secs, 424 Line Err Secs, 0 Degraded Mins,

3547 Errored Secs, 31 Bursty Err Secs, 11 Severely Err Secs, 0 Unavail

Thanks in advance.

Champika

[scottmac]

If this is one interface on a dual WIC, only one of the interfaces can receive line clocking, the other must use "loop:" derived from the interface that is receiving the line clocking as a source.

Good Luck

Scott

[janith]

Hi

I have a single VWIC-1MFT-E1 card with a AIM. I have done the following

network-clock-participate wic 0

network-clock-select 1 E1 0/0

This is to synchronize the clock received from the line to that of the AIM card.

Now I have the following problem. The Slips have stopped but the line code violations and path code violations are increasing

ER26-AUH-NAJDA#sh controllers e1 0/0

E1 0/0 is up.

Applique type is Channelized E1 - balanced

No alarms detected.

alarm-trigger is not set

Version info Firmware: 20040408, FPGA: 11, spm_count = 0

Framing is CRC4, Line Code is HDB3, Clock Source is Line.

CRC Threshold is 320. Reported from firmware is 0.

Data in current interval (19 seconds elapsed):

58 Line Code Violations, 50 Path Code Violations

0 Slip Secs, 0 Fr Loss Secs, 19 Line Err Secs, 0 Degraded Mins

19 Errored Secs, 12 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs

The SP is using linecode of HDB3 and framing of CRC4.

Any help would be appreciated.

Thanks

Champika