Hey,
does anyone know of issues with running a BERT test on these new V3 WIC cards. This is running on a 3945.
When running a BERT test I cannot see the BERT total k bits increasing, even though the BERT is set and running.
See below: (This is only an example) Generally we would have a hard Loop Plug in the WIC card or end of wiring.
T1 0/1/0 is up. (Local Line Loopback)
Applique type is Channelized T1
Cablelength is long 0db
DSX1 BERT pattern : 2^20-QRSS
DSX1 BERT sync : no sync
DSX1 BERT sync count : 1
DSX1 BERT interval : 5
DSX1 BERT time remain : 260
DSX1 BERT total errs : 0
DSX1 BERT total k bits: 0
DSX1 BERT errors (last): 0 {-- Does not increse.
DSX1 BERT k bits (last): 0
Last clearing of BERT counters never
Receiver has no alarms.
alarm-trigger is not set
Soaking time: 3, Clearance time: 10
AIS State:Clear LOS State:Clear LOF State:Clear
Version info FPGA Rev: 08121917, FPGA Type: PRK4
Framing is ESF, FDL is ansi & att, Line Code is B8ZS, Clock Source is Line.
CRC Threshold is 320. Reported from firmware is 320.
Data in current interval (691 seconds elapsed):
3 Line Code Violations, 3 Path Code Violations
0 Slip Secs, 0 Fr Loss Secs, 3 Line Err Secs, 0 Degraded Mins
3 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
Data in Interval 1:
0 Line Code Violations, 8 Path Code Violations
0 Slip Secs, 581 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 581 Unavail Secs
Total Data (last 1 15 minute intervals):
0 Line Code Violations, 8 Path Code Violations,
0 Slip Secs, 581 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins,
0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 581 Unavail Secs
T1 0/1/0 is up. (Local Line Loopback)
Applique type is Channelized T1
Cablelength is long 0db
DSX1 BERT pattern : 2^20-QRSS
DSX1 BERT sync : no sync
DSX1 BERT sync count : 1
DSX1 BERT interval : 5
DSX1 BERT time remain : 260
DSX1 BERT total errs : 0
DSX1 BERT total k bits: 0
DSX1 BERT errors (last): 0
DSX1 BERT k bits (last): 0
Last clearing of BERT counters never
Receiver has no alarms.
alarm-trigger is not set
Soaking time: 3, Clearance time: 10
AIS State:Clear LOS State:Clear LOF State:Clear
Version info FPGA Rev: 08121917, FPGA Type: PRK4
Framing is ESF, FDL is ansi & att, Line Code is B8ZS, Clock Source is Line.
CRC Threshold is 320. Reported from firmware is 320.
Data in current interval (691 seconds elapsed):
3 Line Code Violations, 3 Path Code Violations
0 Slip Secs, 0 Fr Loss Secs, 3 Line Err Secs, 0 Degraded Mins
3 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
Data in Interval 1:
0 Line Code Violations, 8 Path Code Violations
0 Slip Secs, 581 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 581 Unavail Secs
Total Data (last 1 15 minute intervals):
0 Line Code Violations, 8 Path Code Violations,
0 Slip Secs, 581 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins,
0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 581 Unavail Secs
So the only way to test this is by placing the interface into HDLC mode and assigning an IP address and running pings, which in general are not as good as BERT tests.
Does anyone know of any issues or documention that I can read to over come this issue and ensure that BERT's are been run successfully.
