Is there something special about these cards and pinging against a hard loop.
We have all the channels mapped and have the serial interface up/up looped. We do the normal ping my own ip to test the cable. It consitantly gets loses. We move the loop plug all the way to the router itself and get the same errors.
I have since tried multiple 2811 and 1841 routers at various code levels and have tried a number of different vwic-2mft-t1 cards all with the same result.
Pinging my own address against a loop has always been the method I have used to test ciruits but I can't get it to work with these cards.
The configurations are now as simple as they can be. A channel group maping all the channels and the serial port with a point to point ip address on it.
Hard to say which options we have not changed. Clocking seems to make no difference.
If you're using Frame-Relay encaps, have you created a Frame-relay map to the local interface?
Otherwise, the router tries to send the frame to the other end, which (if not looped and is ooperational) would send the frame back to you (but the ping time would be ~double).
Without the local map, the frame is sent to the other side, but there's nothing there to receive and return the frame.
Just guessing ....
Slowly getting somewhere.
It appears to be related to the dependancy between the interface ports to share a clock.
It seems to run agains a hard loop if you boot the router and loop a single port. If you loop both ports hard or have a live circuit in one and hard loop the other it gets confused. Not the best if you have to test a single circuit and do not want to affect the other one. Will post if I find a way to get past this.
You are correct that both links on the card need to share a clock, but I dont see any reason why you cant get around this with 'clock source internal'.
If you have a clock coming in one port from your telco, the VWIC will sync its own clock to this one. Issuing a 'clock source internal' on the 2nd port will cause its TX clock to be the same as the clock on the 1st port, and there wont be an issue.
Also, whether you have another T1 coming in with a clock or not, having 'clock source line' on a hard looped port will cause errors. The port will try to recover a clock from the line, of which there isn't any.