Cat 9300 series switches

[peterdervan]

Hi,

Historically, there used to be an allocation of ports on a switch assigned to an ASIC within the switch. Various commands, eg. show int gig1/0/1 cap, for example, might indicate which group of ports were assigned / using the same ASIC. 

I was reading the current 9300 series architecture white paper, and I see mention of UADP asic, and 6 rings internally etc, but I'm not sure if there is still an allocation of ports per a dedicated asic, or not (maybe just one common asic these days?).

Could anyone advise on current (eg. 9300) switches in regards to this topic? I am trying to analyse port & BW requirements from an Infra team, to decide if there is any switch limitations that I should be wary of (ie. cable up high BW devices to different ASICs for example).

Any help would be great. Thanks

[Reza Sharifi]

Hi,

Your understanding is correct. Depending on the switch model, they use 1x UADP chipset (ASIC 0) or 2x UADP (ASIC 0 and 1). See Figures 1-11

https://www.cisco.com/c/en/us/products/collateral/switches/catalyst-9300-series-switches/nb-06-cat9300-architecture-cte-en.html

HTH

[Joseph W. Doherty]

From what I recall (?) reading 9k architecture papers, every port has equal access to resources so that there's no advantage to try to distribute port loading.

However, unknown what happens if a particular ASIC fails.  I.e. a group of ports fail with it, or whether there's potential service degradation to all other ports.