12-07-2012 07:32 AM - edited 03-07-2019 10:27 AM
Hi experts,
I've a question about the implementation of destination MAC address filtering for ethernet interfaces. For instance on a C3745 fast0/0
Nettuno#sh controll f0/0
Interface FastEthernet0/0
Hardware is GT96K FE ADDR: 658BB044, FASTSEND: 60648690, MCI_INDEX: 0
DIST ROUTE ENABLED: 0Route Cache Flag: 11
GPIO 2 CONF= 7FFF7FFF GPIO 2 IO= 3D003D CIU arbit = 80F002BD
PHY add register = 0x20 PHY data register = 0xE204780
Port Conf Reg= 0x80 ENABLE HT8K HMOD0
Port Conf Ex Reg= 0xCD00
TX1:1 RXPRI=DE(00) ~FLCNTL ~FLNKP MFL64KB E
Port Com Reg= 0x0
Port Status Reg= 0xB 100MB FDPX FCTL EN LNK UP ~PAUSED TX oFF
Serial Param Reg= 0x218823 Hash table pointer= 0x71A5B60
Source ADDR L= 0xD2F0 Source ADDR H= 0x7B35B
SDMA conf reg= 0x223C RETX 15 RX BE TX BE FRINT BSIZE 4
SDMA com reg= 0x1010080 SRT TXL STP TXH EN RX
IMASK= 0x90003DCD ICause= 0x0
Serial 0 mask 30000F3Serial 0 cause 0
IpDiffservP0L= 0x0 IpDiffservP0H= 0x0 IpDiffservP1L= 0x0 IpDiffservP1H= 0x0
IP VLAN TAG PRI= 0xF0CC IP VLAN TAG PRI= 0xF0CC
First rxd Q0= 0x71E5D20 Curr rxd Q0= 0x71E5D20
First rxd Q1= 0x71E6040 Curr rxd Q1= 0x71E6040
First rxd Q2= 0x71E64A0 Curr rxd Q2= 0x71E64A0
First rxd Q3= 0x71E6900 Curr rxd Q3= 0x71E6900
First txd Q0= 0x71E7300 First txd Q1= 0x71E75A0
gt96kfe_instance=0x658BCAE4, registers=0xB4084800
RxRing entries=64, tx ring entries=128
RxR0=0x 71E5BE0, RxR1=0x 71E6040, RxR2=0x 71E64A0, RxR3=0x 71E6900
Malloc RxR0=0x 71E5BE0, RxR1=0x 71E6040, RxR2=0x 71E64A0, RxR3=0x 71E6900
SDOW RxR0=0x658BD08C, RxR1=0x658BD1C0, RxR2=0x658BD2F4, RxR3=0x658BD428
HEAD RxR0=0x12, RxR1=0x0, RxR2=0x0, RxR3=0x0
TAIL RxR0=0x0, RxR1=0x0, RxR2=0x0, RxR30x0
tx_limited=0(128)
TxR0=0x 71E6D60, TxR1=0x 71E75A0
COUNT TxR0=0x0, TxR1=0x0
Head TxR0=0x59, TxR1=0x0 Tail TxR0=0x59, TxR1=0x0
PHY registers:
Register 0x00: 1000 782D 0013 78E2 01E1 41E1 0007 0000
Register 0x08: 0000 FFFF FFFF FFFF FFFF FFFF FFFF FFFF
Register 0x10: 0000 4780 0000 0000 041A 0000 0000 0000
Register 0x18: 0000 0000 00C8 0000 FFFF 0000 0400
Bytes_recvd 527472993 Bytes_sent 2569062024 Frames_recvd 240422641 Frames_sent 257948602
total_bytes_RX 527472993 Total_frames_RX 240422641 Bcast_frames_recvd 34893
Mcast_frames_RX 363211 CRC_err 0 Ovr_sized_frames 0
Fragments 0 Jabber 0 collision 0
Late_collision 0 64B frame 140414097; 65_127B_frames 218379030
128_255B_frames 34607689 256_511B_frames 16382658 512_1023B_frames 11281852
1023_maxB_frames 77305917 Rx_error 0 Dropped_frames 0
Mcast_frames_tx 11477 Bcast_frames_tx 199847 Sml_frame_recvd 0
Software MAC address filter(hash:length/addr/mask/hits): <----------------------
0x00: 0 ffff.ffff.ffff 0000.0000.0000 0
0x43: 0 0007.b35b.d2f0 0000.0000.0000 0
0xC0: 0 0100.0ccc.cccc 0000.0000.0000 0
======= Driver Counters =======
Number of Transmitter Hang = 0
tx_more_col_err= 0 tx_one_col_err= 0
tx_exc_collision_err= 0 tx_late_collision_err= 0
tx_underrun_err= 0 tx_error_intr= 0
rx_soft_overflow_err= 0 rx_overflow_err= 0
we can see it does exist a "Software MAC address filter" to match accepted MAC addresses (broadcast, BIA MAC and CDP)
Now I'd like to know if destination MAC address filtering is implemented at software level (e.g. by interface driver code running on the CPU ) or in hardware by the interface controller chip (GT96K here)
My question is related to router performance (just to understand if the router's CPU is involved every time an ethernet frame is received by the interface)....
Thanks.
Solved! Go to Solution.
12-07-2012 08:01 AM
Hello Carlo,
the MAC address filter should be programmed in the controller and it says what frames should be received on the interface.
The MAC address filter is programmed with unicast, broadcast and multicast entries depending on the router configuration (for example OSPF will use two entries, EIGRP one entry. PIM one entry and so on).
This MAC address filter has a finite size and it was 32 entries on C7500 and C12000.
We had a trouble with the use of subinterfaces on C7500 and C12000 where we reached this limit because each HSRP group consumed one entry on the device acting as HSRP active.
To solve our issue we had to distribute the HSRP active role for the different groups on two devices.
So I would say the most important aspect is the finite size of the filter.
Main router cpu should not be involved. It should be the NIC controller that implements the MAC address filter.
Hope to help
Giuseppe
12-07-2012 08:01 AM
Hello Carlo,
the MAC address filter should be programmed in the controller and it says what frames should be received on the interface.
The MAC address filter is programmed with unicast, broadcast and multicast entries depending on the router configuration (for example OSPF will use two entries, EIGRP one entry. PIM one entry and so on).
This MAC address filter has a finite size and it was 32 entries on C7500 and C12000.
We had a trouble with the use of subinterfaces on C7500 and C12000 where we reached this limit because each HSRP group consumed one entry on the device acting as HSRP active.
To solve our issue we had to distribute the HSRP active role for the different groups on two devices.
So I would say the most important aspect is the finite size of the filter.
Main router cpu should not be involved. It should be the NIC controller that implements the MAC address filter.
Hope to help
Giuseppe
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