sh network-clocks
Network Clock Configuration
---------------------------
Priority Clock Source Clock State Clock Type
1 E1 0/0/0 GOOD E1
10 Backplane GOOD PLL
Current Primary Clock Source
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Priority Clock Source Clock State Clock Type
1 E1 0/0/0 GOOD E1
Sh controller e1
E1 0/0/0 is up.
Applique type is Channelized E1 - balanced
No alarms detected.
alarm-trigger is not set
Version info FPGA Rev: 08121917, FPGA Type: PRK4
Framing is CRC4, Line Code is HDB3, Clock Source is Line.
International Bit: 1, National Bits: 11111
Data in current interval (353 seconds elapsed):
0 Line Code Violations, 0 Path Code Violations
0 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
Total Data (last 24 hours)
1 Line Code Violations, 1790 Path Code Violations,
1 Slip Secs, 90 Fr Loss Secs, 1 Line Err Secs, 0 Degraded Mins,
44 Errored Secs, 4 Bursty Err Secs, 34 Severely Err Secs, 95 Unavail Secs
Even I got so many Input and CRC errors in Sh Inter se 0/0/0:15....
So please tell me excat solution....to resolve this issue
