CPU reset reason = 8, why ROMmon software display it?

[alexis.au.chairez]

Hi everyone.

Already i'm working whit a A99-12X100GE line card, 
During boot up into ROMmon, serial console show as follow

Somebody may help me to know why board restar twice?

Thanks in advance

Booting Management Processor

skyhammer_init()

NVSRAM device ID 681C8A0

hwlog_init() : INFO : NVSRAM RTC oscillator already disabled.

Power down on card removal (OIR power down) is enabled

PLX PEX configured from SEEPROM revision 0.3

configure NTB

Assign bus number

configure NTB

debug NT0 bar size 400000

skyhammer_morra0_init()

Morra 0 PCIe autonomous register restoration enabled.

skyhammer_sideswipe0_init()

Sideswipe 0 PCIe autonomous register restoration enabled.

skyhammer_morra1_init()

Morra 1 revision 1.2

loading GPIO tables for rev greater than or equal to 6

DB Revision : 6

PLX PEX configured from SEEPROM revision 0.1

Morra 1 PCIe autonomous register restoration enabled.

skyhammer_sideswipe1_init()

Sideswipe 1 PCIe autonomous register restoration enabled.

Booting Main Processor

Switching to line card CPU console

 [=3h[=3h [=3h[=3h[=3h

ASR9K Init Starting ASR9k initialization ...

Reading both MB and DB cookie

Board Type:0x3d02c3

Non Powerglide & STLRD Stetting i2c block 3

The base address of i2c_mux4to1 is at d2300800

zl init Skyhammer

Initializing Zl clock to 156MHz

Missing Parameter SERVER_URL

##########################################################

System Bootstrap, Version 9.30 [ASR9K x86 ROMMON],

Copyright (c) 1994-2019 by Cisco Systems, Inc.

Compiled on Tue 07/16/2019 14:52:26.92

BOARD_TYPE             : 0x3d02c3

Rommon                 : 9.30 (Primary)

IPU FPGA(PL)           : 0.16.0 (Primary)

IPU INIT(HW.FPD)       : 1.89.0

IPU FSBL(BOOT.BIN)     : 1.112.0

IPU LINUX(IMAGE.FPD)   : 1.112.0

MORRA MB FPGA          : 1.2.0

SIDESWIPE MB FPGA      : 1.2.0

CBC0                   : Part 1=46.6, Part 2=46.6, Act Part=2

Product Number         : A99-12X100GE

Slot Number            : 0

==========================================================

Got EMT Mode as IOS-XR Boot

Since response is not received for os_type, switch to IOS-XR 32 bit

Got CBC OS type as IOS-XR 32 bit

Unexpected value, Got Boot Mode=65535

Booting IOS-XR (32 bit Classic XR) - Press Ctrl-c to stop

Checking OS type.

CBC OS type detected emt_mode 3 CBC OS type as 2

Set CBC OS type IOS-XR 32 bit, EMT IOS-XR Boot to CBC

[PCIe Link] HOOPER_0 status: (up)0x7011 (dw)0x1011 <OK>

[PCIe Link] HOOPER_1 status: (up)0x7011 (dw)0x1011 <OK>

[PCIe Link] HOOPER_2 status: (up)0x7011 (dw)0x1011 <OK>

[PCIe Link] HOOPER_3 status: (up)0x7011 (dw)0x1011 <OK>

[PCIe Link] NIAN0_0 status: (up)0x2082 (dw)0x1082 <OK>

MAC Init: need programming MAC address



SNP MAC Init: bus 26 port 0

SNP MAC Init: bus 26 port 1

SNP MAC Init: bus 29 port 0

MAC Init SNP: PXE port found

SNP MAC Init: MAC address updated.

SNP MAC Init: bus 29 port 1



ASR9K FPD Starting ASR9k fpd check ...

Connecting all

Located CiscoSec Protocol

Internal EFI ShellUEFI Interactive Shell v2.1

EDK II

UEFI v2.40 (INSYDE Corp., 0x55150021)

Mapping table

      FS0: Alias(s):HD72a0a1:;BLK1:

PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x0,0x0,0x0)/HD(1,MBR,0x00000000,0x20,0x68F7E0)

      FS1: Alias(s):HD72a0a2:;BLK2:

PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x0,0x0,0x0)/HD(2,MBR,0x00000000,0x68F800,0x65E800)

      FS2: Alias(s):HD72a0a3:;BLK3:

PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x0,0x0,0x0)/HD(3,MBR,0x00000000,0xCEE000,0x1CF5000)

     BLK0: Alias(s):

PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x0,0x0,0x0)

Press ESC in 5 seconds to skip startup.nsh or any other key to continue.Press ESC in 4 seconds to skip startup.nsh or any other key to continue.Press ESC in 3 seconds to skip startup.nsh or any other key to continue.Press ESC in 2 seconds to skip startup.nsh or any other key to continue.Press ESC in 1 seconds to skip startup.nsh or any other key to continue.

Enter efi_start

Enter vx86rmon_efi_start image_handle 0x65244398 system_table 0x684fef18

Entering vx86rmon_init

intializing Tomahawk LC RomMon

LC will boot from RP1/RSP1.

Reading both MB and DB cookie

Board Type:0x3d02c3

Non Powerglide & STLRD Settting i2c block 3

The base address of i2c_mux4to1 is at d2300800

zl init Skyhammer

Initializing Zl clock to 156MHz

##########################################################

System Bootstrap, Version 9.30 [ASR9K x86 ROMMON],

Copyright (c) 1994-2019 by Cisco Systems, Inc.

Compiled on Tue 07/16/2019 14:52:26.92

BOARD_TYPE             : 0x3d02c3

Rommon                 : 9.30 (Primary)

IPU FPGA(PL)           : 0.16.0 (Primary)

IPU INIT(HW.FPD)       : 1.89.0

IPU FSBL(BOOT.BIN)     : 1.112.0

IPU LINUX(IMAGE.FPD)   : 1.112.0

MORRA MB FPGA          : 1.2.0

SIDESWIPE MB FPGA      : 1.2.0

CBC0                   : Part 1=46.6, Part 2=46.6, Act Part=2

==========================================================

CPU reset reason = 8 (CPU_RESET_WDOG_POR)

B1:D0:F0: ASPM=0x420000

B1:D0:F1: ASPM=0x420000

B1:D0:F2: ASPM=0x420000

B1:D0:F3: ASPM=0x420000

B1:D0:F4: ASPM=0x420000

B2:D1:F0: ASPM=0xa0420000

B2:D8:F0: ASPM=0xa0430000

B18:D0:F0: ASPM=0x430000

Morra DB access problem, no fabric asic link check

morra1_rev_data=0xffffffff

DRAM Frequency: 2133 MHz

DRAM Frequency: 2133 MHz

Memory Size: 32768 MB

UEFI Interactive Shell v2.1

EDK II

UEFI v2.40 (INSYDE Corp., 0x55150021)

Mapping table

      FS0: Alias(s):HD72a0a1:;BLK1:

PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x0,0x0,0x0)/HD(1,MBR,0x00000000,0x20,0x68F7E0)

      FS1: Alias(s):HD72a0a2:;BLK2:

PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x0,0x0,0x0)/HD(2,MBR,0x00000000,0x68F800,0x65E800)

      FS2: Alias(s):HD72a0a3:;BLK3:

PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x0,0x0,0x0)/HD(3,MBR,0x00000000,0xCEE000,0x1CF5000)

     BLK0: Alias(s):

PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x0,0x0,0x0)

Mapping table

      FS0: Alias(s):HD72a0a1:;BLK1:

PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x0,0x0,0x0)/HD(1,MBR,0x00000000,0x20,0x68F7E0)

      FS1: Alias(s):HD72a0a2:;BLK2:

PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x0,0x0,0x0)/HD(2,MBR,0x00000000,0x68F800,0x65E800)

      FS2: Alias(s):HD72a0a3:;BLK3:

PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x0,0x0,0x0)/HD(3,MBR,0x00000000,0xCEE000,0x1CF5000)

     BLK0: Alias(s):

PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x0,0x0,0x0)

UEFI Interactive Shell v2.1

EDK II

UEFI v2.40 (INSYDE Corp., 0x55150021)

Mapping table

      FS0: Alias(s):HD72a0a1:;BLK1:

PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x0,0x0,0x0)/HD(1,MBR,0x00000000,0x20,0x68F7E0)

      FS1: Alias(s):HD72a0a2:;BLK2:

PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x0,0x0,0x0)/HD(2,MBR,0x00000000,0x68F800,0x65E800)

      FS2: Alias(s):HD72a0a3:;BLK3:

PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x0,0x0,0x0)/HD(3,MBR,0x00000000,0xCEE000,0x1CF5000)

     BLK0: Alias(s):

PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x0,0x0,0x0)

Mapping table

      FS0: Alias(s):HD72a0a1:;BLK1:;disk0:

PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x0,0x0,0x0)/HD(1,MBR,0x00000000,0x20,0x68F7E0)

UEFI Interactive Shell v2.1

EDK II

UEFI v2.40 (INSYDE Corp., 0x55150021)

Mapping table

      FS0: Alias(s):HD72a0a1:;BLK1:

PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x0,0x0,0x0)/HD(1,MBR,0x00000000,0x20,0x68F7E0)

      FS1: Alias(s):HD72a0a2:;BLK2:

PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x0,0x0,0x0)/HD(2,MBR,0x00000000,0x68F800,0x65E800)

      FS2: Alias(s):HD72a0a3:;BLK3:

PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x0,0x0,0x0)/HD(3,MBR,0x00000000,0xCEE000,0x1CF5000)

     BLK0: Alias(s):

PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x0,0x0,0x0)

Mapping table

      FS1: Alias(s):HD72a0a2:;BLK2:;disk0a:

PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x0,0x0,0x0)/HD(2,MBR,0x00000000,0x68F800,0x65E800)

UEFI Interactive Shell v2.1

EDK II

UEFI v2.40 (INSYDE Corp., 0x55150021)

Mapping table

      FS0: Alias(s):HD72a0a1:;BLK1:

PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x0,0x0,0x0)/HD(1,MBR,0x00000000,0x20,0x68F7E0)

      FS1: Alias(s):HD72a0a2:;BLK2:

PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x0,0x0,0x0)/HD(2,MBR,0x00000000,0x68F800,0x65E800)

      FS2: Alias(s):HD72a0a3:;BLK3:

PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x0,0x0,0x0)/HD(3,MBR,0x00000000,0xCEE000,0x1CF5000)

     BLK0: Alias(s):

PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x0,0x0,0x0)

Mapping table

      FS2: Alias(s):HD72a0a3:;BLK3:;usb:

PciRoot(0x0)/Pci(0x1F,0x2)/Sata(0x0,0x0,0x0)/HD(3,MBR,0x00000000,0xCEE000,0x1CF5000)

Valid Flash Device returned -

Device Type 3

Id 1620512, ExtId 0, Size 8, VendorName Micron DeviceName N25Q128A

The value of autoc is 0xc09c2205

The value of autoc is 0xc09c2205

[NIANTIC] PCIE LINK UP

[Niantic] INTEL EOBC LINK UP

rommon 1 >

rommon 1 >

rommon 1 >

[mivens]

It's a Watchdog timeout causing the linecard to be power cycled as per
https://community.cisco.com/t5/xr-os-and-platforms/asr9k-5-1-3-is-there-somewhere-that-provies-us-a-list-of-reset/m-p/2728638/highlight/true#M5894 

What version of IOS-XR are you trying to get the LC to work with and on what hardware (post "show platform" output)?
Is this the first time you have tried to get the A99-12X100GE to work with that hardware/software combination?

[alexis.au.chairez]

Thanks for quick replay.

I'm using IOS-XR 32 bit Classic XR, I start to diagnose these types of products.

Actually I'm doing diagnostic test using a test sequence. During boot test sequence is waiting for catch a rommon promt, however, unit under test reset twice and time-out expired. I just want to know if CPU_RESET_REASON 8 act out a hardware/software issue whit CPU or microcontroller. In that case, is there any document that can help me to understand better this CPU reset reason?

Thanks in advance.

[mivens]

The watchdog timeout is most likely a symptom of the card not booting in a timely fashion, not the root-cause.

The first thing to do is to confirm the software/hardware combination is supported for that card. Hence the previous questions (which I don't believe have been answered) about which XR version is being used and what other hardware is in the router.