DRAM Parity enabled vs disabled ??

[s.uslay]

I have two 3640s, sh version outputs show different "Parity" settings.. Ayyone knows the difference ?

txs

Serhat

cisco 3640 (R4700) processor (revision 0x00) with 59392K/6144K bytes of memory.

Processor board ID 24396934

R4700 CPU at 100Mhz, Implementation 33, Rev 1.0

DRAM configuration is 64 bits wide with parity enabled.

cisco 3640 (R4700) processor (revision 0x00) with 59392K/6144K bytes of memory.

Processor board ID 26858562

R4700 CPU at 100Mhz, Implementation 33, Rev 1.0

DRAM configuration is 64 bits wide with parity disabled.

[Kevin Dorrell]

It depends on the DRAM chips. You can read all about 3600 memory options at:

http://www.cisco.com/warp/public/63/36xx-arch.html#memory-details

In particular, note the paragraph:

"By default, the 3640 and 3620 ship with non-parity DRAM SIMMS, but parity SIMMs are supported if all banks contain SIMMs that have parity enabled. If parity SIMMs are mixed in a system with non-parity SIMMs, the parity function is not supported on any of the SIMMs. Only certain combinations of DRAM SIMMS are permitted."

Kevin Dorrell

Luxembourg

[s.uslay]

Hi Kevin,

I was wondering if there is any advantage using "parity enabled" SIMMS over the other, but would not think so after reading your link.

txs

serhat

[Kevin Dorrell]

Not really. Gone are the days when memory was so unreliable that it had to check the integrity every byte. If there are memory problems, they are usually detected on power-on.

Kevin Dorrell

Luxembourg