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Difference between "Sh controller t3" and "sh controller serial x/x"

josephjthomas
Level 1
Level 1

What is the difference between the commands "Sh controller t3" and "sh controller serial x/x" ?

They are for the same controller but give different outputs.

XXXXXXXXX>sh controllers t3

T3 1/0 is up.

  Applique type is Subrate T3

  No alarms detected.

  MDL transmission is disabled

  FEAC code received: No code is being received

  Framing is C-BIT Parity, Line Code is B3ZS, Clock Source is Internal

  Data in current interval (320 seconds elapsed):

     0 Line Code Violations, 0 P-bit Coding Violation

     0 C-bit Coding Violation, 0 P-bit Err Secs

     0 P-bit Severely Err Secs, 0 Severely Err Framing Secs

     0 Unavailable Secs, 0 Line Errored Secs

     0 C-bit Errored Secs, 0 C-bit Severely Errored Secs

  Total Data (last 24 hours)

     0 Line Code Violations, 0 P-bit Coding Violation,

     0 C-bit Coding Violation, 0 P-bit Err Secs,

     0 P-bit Severely Err Secs, 0 Severely Err Framing Secs,

     0 Unavailable Secs, 0 Line Errored Secs,

     0 C-bit Errored Secs, 0 C-bit Severely Errored Secs


================================================

XXXXXXXXX>sh controllers serial 1/0

Interface Serial1/0

Hardware is DSXPNM GT96K

idb at 0x70A20B20, driver data structure at 0x675FA45C

GT96K Port Used 2, SCC Num 2

MPSC Registers:

MMCR_L=0x001B04C0, MMCR_H=0x40000000, MPCR=0x00000000

CHR1=0x00FE007E, CHR2=0x00000000, CHR3=0x000011E2, CHR4=0x00000000

CHR5=0x00000000, CHR6=0x00000000, CHR7=0x00000000, CHR8=0x00000000

CHR9=0x00000000, CHR10=0x00003008, CHR11=0x0083F83C

SDMA Registers:

SDC=0x00003301, SDCM=0x00000080, SGC=0x00000000

CRDP=0x2E568530, CTDP=0x2E568CC0, FTDB=0x2E568CC0

BRG Conf Register=0x00480000

Rx Clk Routing Register=0x00000800 Tx Clk Routing Register=0x00000900

Main Routing Register (MRR) addr=0x4B701A00, val=0x00FFFE3F

GPP Registers:

Conf =0x0000007F, Io =0x00000006, Data =0x7E7E7E47, Level =0x00000000

Conf0=0x0       , Io0=0x0       , Data0=0x7E7EFFFF, Level0=0x0

SUBRATE FPGA Registers (Clear T3/E3):

24674 input aborts on receiving flag sequence

0 throttles, 0 enables

11530 overruns

0 transmitter underruns

0 transmitter CTS losts

349496014 rxintr, 304041902 txintr, 539 rxerr, 0 txerr

0 mpsc_rx, 719 mpsc_rxerr, 0 mpsc_rlsc, 0 mpsc_rhnt, 0 mpsc_rfsc

0 mpsc_rcsc, 719 mpsc_rovr, 0 mpsc_rcdl, 0 mpsc_rckg, 0 mpsc_bper

1 mpsc_txerr, 1 mpsc_teidl, 1 mpsc_tudr, 0 mpsc_tctsl, 0 mpsc_tckg

0 sdma_rx_sf, 0 sdma_rx_mfl, 11530 sdma_rx_or, 24674 sdma_rx_abr, 21520 sdma_rx_no

0 sdma_rx_de, 0 sdma_rx_cdl, 1682864 sdma_rx_ce, 0 sdma_tx_rl, 0 sdma_tx_ur

539 sdma_rx_reserr, 0 sdma_tx_reserr

0 sdma_tx_ur_processed

0 rx_bogus_pkts, rx_bogus_flag FALSE

0 verilink_runts

tx_limited 0, mci_txcount 128, errata19 count1 0, count2 0

txd_incomplete_count = 0

Receive Ring

rxr head (45)(0x2E568530), rxr tail (0)(0x2E568260)

  rmd(2E568260): nbd 2E568270 cmd_sts 80800000 buf_sz 05E00000 buf_ptr 2E586400

  rmd(2E568270): nbd 2E568280 cmd_sts 80800000 buf_sz 05E00000 buf_ptr 2E573800

    <TRUNCATED>   

2 Replies 2

paolo bevilacqua
Hall of Fame
Hall of Fame

Output is different because hardware and circuit have different characteristics.

Howver in most cases the only infromation you are intrested is if the controller status: up or down.

Sh controller t3 is for a Time-Division Multiplexed DS3 usually from the carrier.

sh controller serial x/x is for the serial data side of the circuit.

 

Carrier digital signal circuit vs. Serial Data Circuit

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