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6800 performance and architecture

mikael eriksson
Level 7
Level 7

hey !

I was reading the white papers on 6807-XL, 6880-X and Sup2T and i have some questions. I will start of by apologizing for my bad English.

Many of my questions is about the 6880-X chassi and i have read these white papers 

http://www.cisco.com/c/en/us/products/collateral/switches/catalyst-6880-x-switch/white_paper_c11-728540.html

http://www.cisco.com/c/en/us/products/collateral/switches/catalyst-6500-series-switches/white_paper_c11-696669.html

http://www.cisco.com/c/en/us/products/collateral/switches/catalyst-6807-xl-switch/white_paper_c11-728264.html

 

My understanding is that the switch fabric in 6880-X consists of 24 fabric channels and that every module slot gets 4 of these channels. 1 channel can operate in 40 or 55Gbps depending on the clock frequencies of the SerDes lanes. I also read that only 2 of these channels are active and that 2 are there for future use. This means that every slot can have a switch fabric connection consisting of 80 or 110Gbps. The 6880-X linecards consists of 16 SFP/SFP+ ports but only has a 80Gbps switch fabric connection(2*40Gbps).

1. Is this correct or have i missed something? 

2. Is it possible to configure only 1 line card in performance mode and leave the rest at default?

 

Does anyone know how the fabric channel is chosen on incoming and outgoing flows? If you run 6880-X in VSS you have 4 active fabric channels, how does the flows balance over these 4 fabric channels? Or the 2 fabric channels without VSS. Is it a hashing algorithm similar to etherchannels, like the one used in X6904-40G on the 4*16Gbps internal channels? 

 

These SFP/SFP+ ports is also said to support 40Gbps with a SFP-to-QSFP module but since the port complex is based on the X6904-40G linecard it wont be possible to achieve 40Gbps linerate. Since one flow is loadbalanced over 1 16Gbps internal channel.

3. Is this correct or have i missed something?

 

Looking at the schematics of the port complex i see that the connection between Port ASIC and MUX FPGA consists of 8*6.25Gbps.

4. Is the incoming and outgoing flows loadbalanced over all of these connections or can one flow only use one of these 6.25Gbps connections?

5. If it is loadbalanced does anyone know the hash algorithm?

 

6. Does anyone know if and when there will be 40Gbps linecards to 6807-XL?

7. Does anyone know if the planned 32*10Gbps linecard for 6807-XL will use 4 fabric channels to run all 32 ports in linerate?

 

I hope i have placed this topic in the right section.

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