Hi all,
The Catalyst 9200L switches has a non-blocking architecture?
I have found at documentations that Catalyst 9200 uses UADP 2.0 mini ASIC which has up 100G total bandwidth.
https://community.cisco.com/t5/networking-blogs/uadp-the-powerhouse-of-catalyst-9000-family/ba-p/3764605
In another guide, the information is that "Non-mGig models are powered by a single UADP 2.0 mini ASIC, whereas the mGig" models have two UADP 2.0 mini ASICs".
https://www.cisco.com/c/dam/en/us/products/collateral/switches/catalyst-9000/nb-06-cat9k-ebook-cte-en.pdf
Once, the switch C9200L-48P-4X has 256 Gbps switching capacity with stacking, and not is a non-mGig model, how to it is possible this provide this value of 256 Gbps, with only one UADP 2.0 mini ASIC?
So, the Catalyst 9200L, the SKU model C9200L-48P-4X, has a non-blocking architecture?
Thank you!
Allyson
