11-11-2022 06:10 AM
Hi,
As I understand, Cisco Catalyst 9500-48Y4C switch uses both ASIC and CPU. Particularly, ASIC chip is used for basic switching. Meanwhile, CPU can be used for app-hosting feature (Docker containers). I am wondering whether we can have the interplay between ASIC and CPU so that the containers (processed by CPU) can leverage ASIC performance.
11-11-2022 06:44 AM
- You may find this document informational : https://www.ciscolive.com/c/dam/r/ciscolive/us/docs/2019/pdf/BRKARC-2035.pdf
M.
11-12-2022 02:00 PM
Hi Marce,
Thank you for the comprehensive document. Unfortunately, I could not find the configuration for the interplay between ASIC and CPU in the document.
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