02-22-2017 09:21 AM - edited 03-17-2019 09:37 AM
sh controller t1
T1 0/0/0 is up.
Applique type is Channelized T1
Cablelength is long 0db
No alarms detected.
alarm-trigger is not set
Soaking time: 3, Clearance time: 10
AIS State:Clear LOS State:Clear LOF State:Clear
Version info FPGA Rev: 08121917, FPGA Type: PRK4
Framing is ESF, Line Code is B8ZS, Clock Source is Line.
CRC Threshold is 320. Reported from firmware is 320.
Data in current interval (377 seconds elapsed):
0 Line Code Violations, 0 Path Code Violations
81 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
81 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
Total Data (last 1 15 minute intervals):
0 Line Code Violations, 0 Path Code Violations,
193 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins,
193 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Sec
02-22-2017 10:37 AM
Can you make sure that the line code is matching the one configured by your upstream provider
02-22-2017 11:37 AM
Unless you're on an ISR 4300/4400 where the DSPs are daughter cards per-NIM, also be aware of the clocking domain limitations.
http://www.cisco.com/c/en/us/support/docs/wan/tdm/116050-trouble-tdm-clocking-00.html
If the ISDN PRIs are from multiple providers, or even the same provider but connected to different C.O. equipment, they may not share the same clock source.
05-01-2019 07:00 AM
Hi Rakesh,
As others mentioned this is almost certainly a clocking issue. Were you able to get this resolved?
Are there multiple PRIs?
If so, are all of the PRIs taking Slips & Errored Secs or just one of the PRIs?
What model of router?
Regards,
Dalton Woolsey
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