Re: CPU sdr getting error during boot in cisco catalyst 2960 switch

prashant824173019 · ‎12-02-2020

Dear member

CPU's PCIe SDR Registers--------------------
PE_DLPSET = 00401000
PE_UTLSET1 = 00000000
PE_UTLSET2 = 01010000
PE_PHYSET1 = 720E0000
PE_PHYSET2 = 50600003
PE_RCSSET = 01101000
PE_PHYSTA = 02111000
PE_RCSSTS = 00000000
PE_LOOP = 10000000

hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
PCIE0: link is NOT up.
--------------CPU's PCIe SDR Registers--------------------
PE_DLPSET = 00401000
PE_UTLSET1 = 00000000
PE_UTLSET2 = 01010000
PE_PHYSET1 = 720E0000
PE_PHYSET2 = 50600003
PE_RCSSET = 01101000
PE_PHYSTA = 02111000
PE_RCSSTS = 00000000
PE_LOOP = 10000000

and constantly reboot switch

pls help to me how the fix this error

balaji.bandi · ‎12-02-2020

First i will do Power down and Power up and see if that fix the issue.

Try different IOS if possible,

Most cases - Looks something went wrong, raise TAC case for RMA - if this is part of smartnet contract and still valid.

BB

***** Rate All Helpful Responses *****

How to Ask The Cisco Community for Help

Leo Laohoo · ‎12-02-2020

Console into the switch and post the entire boot-up process.

prashant824173019 · ‎12-02-2020

PSET = 00401000
PE_UTLSET1 = 00000000
PE_UTLSET2 = 01010000
PE_PHYSET1 = 720E0000
PE_PHYSET2 = 50600003
PE_RCSSET = 01101000
PE_PHYSTA = 02111000
PE_RCSSTS = 00000000
PE_LOOP = 10000000

hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
PCIE0: link is NOT up.
--------------CPU's PCIe SDR Registers--------------------
PE_DLPSET = 00401000
PE_UTLSET1 = 00000000
PE_UTLSET2 = 01010000
PE_PHYSET1 = 720E0000
PE_PHYSET2 = 50600003
PE_RCSSET = 01101000
PE_PHYSTA = 02111000
PE_RCSSTS = 00000000
PE_LOOP = 10000000

hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
PCIE0: link is NOT up.
--------------CPU's PCIe SDR Registers--------------------
PE_DLPSET = 00401000
PE_UTLSET1 = 00000000
PE_UTLSET2 = 01010000
PE_PHYSET1 = 720E0000
PE_PHYSET2 = 50600003
PE_RCSSET = 01101000
PE_PHYSTA = 02111000
PE_RCSSTS = 00000000
PE_LOOP = 10000000

hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
PCIE0: link is NOT up.
--------------CPU's PCIe SDR Registers--------------------
PE_DLPSET = 00401000
PE_UTLSET1 = 00000000
PE_UTLSET2 = 01010000
PE_PHYSET1 = 720E0000
PE_PHYSET2 = 50600003
PE_RCSSET = 01101000
PE_PHYSTA = 02111000
PE_RCSSTS = 00000000
PE_LOOP = 10000000

hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO bacy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
PCIE0: link is NOT up.
--------------CPU's PCIe SDR Registers--------------------
PE_DLPSET = 00401000
PE_UTLSET1 = 00000000
PE_UTLSET2 = 01010000
PE_PHYSET1 = 720E0000
PE_PHYSET2 = 50600003
PE_RCSSET = 01101000
PE_PHYSTA = 02111000
PE_RCSSTS = 00000000
PE_LOOP = 10000000

hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
PCIE0: link is NOT up.
--------------CPU's PCIe SDR Registers--------------------
PE_DLPSET = 00401000
PE_UTLSET1 = 00000000
PE_UTLSET2 = 01010000
PE_PHYSET1 = 720E0000
PE_PHYSET2 = 50600003
PE_RCSSET = 01101000
PE_PHYSTA = 02111000
PE_RCSSTS = 00000000
PE_LOOP = 10000000

hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unableie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
PCIE0: link is NOT up.
--------------CPU's PCIe SDR Registers--------------------
PE_DLPSET = 00401000
PE_UTLSET1 = 00000000
PE_UTLSET2 = 01010000
PE_PHYSET1 = 720E0000
PE_PHYSET2 = 50600003
PE_RCSSET = 01101000
PE_PHYSTA = 02111000
PE_RCSSTS = 00000000
PE_LOOP = 10000000

hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
hulc_reset_pcie_asic_phy: Unable to access MDIO backdoor
pcie_init_phy_link: ASIC PHY reset failed
PCIE0: link is NOT up.
--------------CPU's PCIe SDR Registers--------------------
PE_DLPSET = 00401000
PE_UTLSET1 = 00000000
PE_UTLSET2 = 01010000
PE_PHYSET1 = 720E0000
PE_PHYSET2 = 50600003
PE_RCSSET = 01101000
PE_PHYSTA = 02111000
PE_RCSSTS = 00000000
PE_LOOP = 10000000

00:04:37 UTC Mon Jan 2 2006: Unexpected exception to CPUvector 200, PC = 1D2C3A 8
-Traceback= 0x1D2C3A8z 0x1C9DA64z 0x1C9DFE8z 0x1C9F8A0z 0x1D8E024z 0x179B548z 0x 179B714z 0x179B864z 0x495B14z 0x495D4Cz 0x214B2CCz 0x214764Cz

=== Flushing messages (00:04:38 UTC Mon Jan 2 2006) ===

Buffered messages:
Queued messages:
*Jan 2 00:04:38.202: %SYS-3-LOGGER_FLUSHING: System pausing to ensure console d ebugging output.

*Mar 1 00:00:27.210: Read env variable - LICENSE_BOOT_LEVEL =
*Jan 2 00:00:00.849: %IOS_LICENSE_IMAGE_APPLICATION-6-LICENSE_LEVEL: Module nam e = c2960s_lanbase Next reboot level = lanbase and License = lanbase
*Jan 2 00:04:38.082: %Insufficient flash filespace for extended crashinfo.
Cisco IOS Software, C2960S Software (C2960S-UNIVERSALK9-M), Version 15.2(2)E9, R ELEASE SOFTWARE (fc4)
Technical Support: http://www.cisco.com/techsupport
Copyright (c) 1986-2018 by Cisco Systems, Inc.
Compiled Sat 08-Sep-18 14:56 by prod_rel_team

Machine Check Exception (0x0200)!
ESR: 0x00000000
SRR0: 0x017DF5A0 SRR1: 0x00029230 SRR2: 0x01D2C3A8 SRR3: 0x00029230
PLB4A0 - ESRH: 0x00000000 ESRL: 0x00000000 EARH: 0x5F1604EF EARL: 0x7FAFFF91
PLB4A1 - ESRH: 0x00000000 ESRL: 0x00008000 EARH: 0x00000000 EARL: 0xEF502000
SDRAM0 - BESR: 0x00000000 BEARH: 0x00000000 BEARL: 0x00000000
PEGPL0 - ESR: 0x00000000 EARH: 0x00000000 EARL: 0x00000000 EATR: 0x00000000
PEGPL1 - ESR: 0x00000000 EARH: 0x00000000 EARL: 0x00000000 EATR: 0x00000000
PLB42OPB0 - BESR0: 0x00000000 BESR1: 0x00000000
BEARH: 0x00000003 BEARL: 0x3166D411
OPB2PLB40 - BSTAT: 0x00000000 BEARH: 0x00000008 BEARL: 0xFEF57569
AHB - SESR: 0x00000000 SEARU: 0x00000000 SEARL: 0x00000000

CPU Register Context:
Vector = 0x00000200 PC = 0x01D2C3A8 MSR = 0x00029230 CR = 0x39000033
LR = 0x01C9DA64 CTR = 0x02141080 XER = 0x8000007C
R0 = 0x00000000 R1 = 0x03A649E8 R2 = 0x00000000 R3 = 0xEF502000
R4 = 0x00000000 R5 = 0x00000000 R6 = 0x03A64998 R7 = 0x00000000
R8 = 0x032A0000 R9 = 0x031F44B4 R10 = 0x00029230 R11 = 0x031FB064
R12 = 0x39000035 R13 = 0x00000280 R14 = 0x00495D04 R15 = 0x00000000
R16 = 0x00000000 R17 = 0x00000000 R18 = 0x00000000 R19 = 0x00000000
R20 = 0x00000000 R21 = 0x00000000 R22 = 0x00000000 R23 = 0x00000000
R24 = 0x00000000 R25 = 0x03A64AC0 R26 = 0x03297C14 R27 = 0x00000400
R28 = 0xEF502000 R29 = 0x000003E8 R30 = 0x00000000 R31 = 0x00000000

Stack trace:
PC = 0x01D2C3A8, SP = 0x03A649E8
Frame 00: SP = 0x03A64A18 PC = 0x01C9D9D0
Frame 01: SP = 0x03A64A28 PC = 0x01C9DFE8
Frame 02: SP = 0x03A64AB8 PC = 0x01C9F8A0
Frame 03: SP = 0x03A64AF8 PC = 0x01D8E024
Frame 04: SP = 0x03A64B08 PC = 0x0179B548
Frame 05: SP = 0x03A64B28 PC = 0x0179B714
Frame 06: SP = 0x03A64B40 PC = 0x0179B864
Frame 07: SP = 0x03A64B70 PC = 0x00495B14
Frame 08: SP = 0x03A64C78 PC = 0x00495D4C
Frame 09: SP = 0x03A64C80 PC = 0x0214B2CC
Frame 10: SP = 0x00000000 PC = 0x0214764C

Switch uptime is 5 minutes, 8 seconds

cisco WS-C2960S-24TD-L (PowerPC) processor (revision C0) with 131072K bytes of m emory.
Processor board ID FOC1522X0TD

this my entire boot processing

marce1000 · ‎12-02-2020

>...(boot listing provided)

- Machine Check Exception (0x0200)!

As already indicated by others, definitely looks like a serious hardware problem -> RMA

M.

-- Each morning when I wake up and look into the mirror I always say ' Why am I so brilliant ? '
When the mirror will then always repond to me with ' The only thing that exceeds your brilliance is your beauty! '