10-05-2012 03:09 PM - edited 03-07-2019 09:18 AM
Hi everybody
The command show controller cpu-interface according to my book shows the number of packets being forwarded to switch's cpu for processing.
The above cisco links says:
Use the show controllers cpu-interface privileged EXEC command to display the state of the CPU network interface ASIC and the send and receive statistics for packets reaching the CPU.
.
What is CPU network interface Asic? I am familiar with internal registers CPU uses to perform mathematical operation but what is CPU network interface?
I will appreciate your input.
thanks and have a great weekend.
Solved! Go to Solution.
10-05-2012 03:34 PM
Hi Sarah,
Here the output of that commnad from a 3750, since your link is also from a 3750 config reference:
Switch#sh controllers cpu-interface
ASIC Rxbiterr Rxunder Fwdctfix Txbuflos Rxbufloc Rxbufdrain
-------------------------------------------------------------------------
ASIC0 0 0 0 0 0 0
ASIC1 0 0 0 0 0 0
ASIC2 0 0 0 0 0 0
cpu-queue-frames retrieved dropped invalid hol-block stray
----------------- ---------- ---------- ---------- ---------- ----------
rpc 0 0 0 0 0
stp 1 0 0 0 0
ipc 0 0 0 0 0
routing protocol 28312 0 0 0 0
L2 protocol 0 0 0 0 0
remote console 0 0 0 0 0
sw forwarding 0 0 0 0 0
host 7648 0 0 0 0
broadcast 462103 0 0 0 0
cbt-to-spt 0 0 0 0 0
igmp snooping 35916 0 0 0 0
icmp 0 0 0 0 0
logging 0 0 0 0 0
rpf-fail 0 0 0 0 0
dstats 0 0 0 0 0
cpu heartbeat 22302361 0 0 0 0
Supervisor ASIC receive-queue parameters
----------------------------------------
queue 0 maxrecevsize 7E0 pakhead 43EE568 paktail 445EE7C
queue 1 maxrecevsize 7E0 pakhead 46896F4 paktail 3E32E9C
queue 2 maxrecevsize 7E0 pakhead 451AFB0 paktail 4537A14
queue 3 maxrecevsize 7E0 pakhead 4C00264 paktail 4BFFB2C
queue 4 maxrecevsize 7E0 pakhead 46A629C paktail 46C2D00
queue 5 maxrecevsize 7E0 pakhead 4A1EBC4 paktail 4A2CF28
queue 6 maxrecevsize 7E0 pakhead 4BCEE48 paktail 4BEB8AC
queue 7 maxrecevsize 7E0 pakhead 4A66C6C paktail 4A57E34
queue 8 maxrecevsize 7E0 pakhead 4A6DD94 paktail 4A6E4CC
queue 9 maxrecevsize 7E0 pakhead 48A1420 paktail 48A1420
queue A maxrecevsize 7E0 pakhead 487FC98 paktail 4879EC0
queue B maxrecevsize 7E0 pakhead 4C09408 paktail 4C0CA2C
queue C maxrecevsize 7E0 pakhead 48AC004 paktail 48C16E8
queue D maxrecevsize 7E0 pakhead 489D91C paktail 48A0F40
queue E maxrecevsize 0 pakhead 0 paktail 0
queue F maxrecevsize 7E0 pakhead 486E8E0 paktail 486F3B4
Supervisor ASIC exception status
--------------------------------
Receive overrun 00000000 Transmit overrun 00000000
FrameSignatureErr 00000000 MicInitialize 00000002
BadFrameErr 00000000 LenExceededErr 00000000
BadJumboSegments 00000000
Supervisor ASIC Mic Registers
------------------------------
MicDirectPollInfo 80000200
MicIndicationsReceived 00000000
MicInterruptsReceived 00000001
MicPcsInfo 0000001F
MicPlbMasterConfiguration 00000000
MicRxFifosAvailable 00000000
MicRxFifosReady 0000BFFF
MicTimeOutPeriod: FrameTOPeriod: 00000EA6 DirectTOPeriod: 00004000
MicTransmFramesCopied 00000003
MicTxFifosAvailable 0000000E
MicConfiguration: Conf flag: 00000110 Interrupt Flag: 00000008
MicReceiveFifoAssignmen Queue 0 - 7: 33333333 Queue 8 - 15:33333333
MicReceiveFramesReady: FrameAvailable: 00000000 frameAvaiMask: 00000000
MicException:
Exception_flag 00000000
Message-1 00000000
Message-2 00000000
Message-3 00000000
MicIntRxFifo:
ReadPtr 00000780 WritePtr 00000780
WHeadPtr 00000780 TxFifoDepth C0000800
MicIntTxFifo:
ReadPtr 00000FA8 WritePtr 00000FA8
WHeadPtr 00000FA8 TxFifoDepth C0000800
MicDecodeInfo:
Fifo0: address: 03FF5000 asic_num: 00000100
Fifo1: address: 03FF4000 asic_num: 00000101
MicTransmitFifoInfo:
Fifo0: StartPtrs: 0E2C9000 ReadPtr: 0E2C9270
WritePtrs: 0E2C9270 Fifo_Flag: 8A800800
Weights: 001E001E
Fifo1: StartPtrs: 0E027400 ReadPtr: 0E027660
WritePtrs: 0E027660 Fifo_Flag: 89800400
Weights: 000A000A
MicReceiveFifoInfo:
Fifo0: StartPtr: 0E4AA000 ReadPtr: 0E4AAFA0
WritePtrs: 0E4AA000 Fifo_Flag: 8B000060
writeHeaderPtr: 0E4AA000
Fifo1: StartPtr: 0E786800 ReadPtr: 0E786808
WritePtrs: 0E786808 Fifo_Flag: 89800400
writeHeaderPtr: 0E786808
Fifo2: StartPtr: 0E73F000 ReadPtr: 0E73F000
WritePtrs: 0E73F000 Fifo_Flag: 89800400
writeHeaderPtr: 0E73F000
Fifo3: StartPtr: 0E99B800 ReadPtr: 0E99B8C8
WritePtrs: 0E99B8C8 Fifo_Flag: 89800400
writeHeaderPtr: 0E99B8C8
Fifo4: StartPtr: 0E7CE000 ReadPtr: 0E7CE000
WritePtrs: 0E7CE000 Fifo_Flag: 89800400
writeHeaderPtr: 0E7CE000
Fifo5: StartPtr: 0E87A600 ReadPtr: 0E87A600
WritePtrs: 0E87A600 Fifo_Flag: 88800200
writeHeaderPtr: 0E87A600
Fifo6: StartPtr: 0E951C00 ReadPtr: 0E951C00
WritePtrs: 0E951C00 Fifo_Flag: 89800400
writeHeaderPtr: 0E951C00
Fifo7: StartPtr: 0E8C1400 ReadPtr: 0E8C1738
WritePtrs: 0E8C1738 Fifo_Flag: 89800400
writeHeaderPtr: 0E8C1738
Fifo8: StartPtr: 0E92DE00 ReadPtr: 0E92DF10
WritePtrs: 0E92DF10 Fifo_Flag: 88800200
writeHeaderPtr: 0E92DF10
Fifo9: StartPtr: 0E2DB4D8 ReadPtr: 0E2DB4D8
WritePtrs: 0E2DB4D8 Fifo_Flag: 82800008
writeHeaderPtr: 0E2DB4D8
Fifo10: StartPtr: 0E817800 ReadPtr: 0E817860
WritePtrs: 0E817860 Fifo_Flag: 88800200
writeHeaderPtr: 0E817860
Fifo11: StartPtr: 0E2C8F00 ReadPtr: 0E2C8F00
WritePtrs: 0E2C8F00 Fifo_Flag: 86800080
writeHeaderPtr: 0E2C8F00
Fifo12: StartPtr: 0E844800 ReadPtr: 0E844B00
WritePtrs: 0E844800 Fifo_Flag: 89000100
writeHeaderPtr: 0E844800
Fifo13: StartPtr: 0E4A9E80 ReadPtr: 0E4A9E80
WritePtrs: 0E4A9E80 Fifo_Flag: 86800080
writeHeaderPtr: 0E4A9E80
Fifo14: StartPtr: 00000000 ReadPtr: 00000000
WritePtrs: 00000000 Fifo_Flag: 00800000
writeHeaderPtr: 00000000
Fifo15: StartPtr: 0E027940 ReadPtr: 0E027958
WritePtrs: 0E027958 Fifo_Flag: 84800020
writeHeaderPtr: 0E027958
===========================================================
Complete Board Id:0x0068
===========================================================
Switch# show controller cpu-interface
So, this command is all about queue-frames retrieved dropped by the CPU.
HTH
Reza
10-06-2012 05:12 AM
Hello Sarah,
you are going very deep in your studies of TBSHOOT!
>> What is CPU network interface Asic? I am familiar with internal registers CPU uses to perform mathematical operation but what is CPU network interface?
This referes to the internal anatomy of a multilayer switch:
traffic arrives on external ports. The ports are divided in groups. Each group of port is managed by an ASIC chip that is specialized hardware. Each ASIC chip needs to interface to the main cpu in order to be able to send and receive packets that is to send packets that need to be process switched and to receive the responses from the main cpu.
So you can imagine a small internal network inside the switch that interconnects the ASICs that manage the port groups to the main cpu.
Another ASIC may act as front-end between port groups ASIC chips and the main cpu, so you get a cpu network interface ASIC.
My guess is that ASIC0, ASIC1 and so on are the port groups ASICs
Hope to help
Giuseppe
10-05-2012 03:34 PM
Hi Sarah,
Here the output of that commnad from a 3750, since your link is also from a 3750 config reference:
Switch#sh controllers cpu-interface
ASIC Rxbiterr Rxunder Fwdctfix Txbuflos Rxbufloc Rxbufdrain
-------------------------------------------------------------------------
ASIC0 0 0 0 0 0 0
ASIC1 0 0 0 0 0 0
ASIC2 0 0 0 0 0 0
cpu-queue-frames retrieved dropped invalid hol-block stray
----------------- ---------- ---------- ---------- ---------- ----------
rpc 0 0 0 0 0
stp 1 0 0 0 0
ipc 0 0 0 0 0
routing protocol 28312 0 0 0 0
L2 protocol 0 0 0 0 0
remote console 0 0 0 0 0
sw forwarding 0 0 0 0 0
host 7648 0 0 0 0
broadcast 462103 0 0 0 0
cbt-to-spt 0 0 0 0 0
igmp snooping 35916 0 0 0 0
icmp 0 0 0 0 0
logging 0 0 0 0 0
rpf-fail 0 0 0 0 0
dstats 0 0 0 0 0
cpu heartbeat 22302361 0 0 0 0
Supervisor ASIC receive-queue parameters
----------------------------------------
queue 0 maxrecevsize 7E0 pakhead 43EE568 paktail 445EE7C
queue 1 maxrecevsize 7E0 pakhead 46896F4 paktail 3E32E9C
queue 2 maxrecevsize 7E0 pakhead 451AFB0 paktail 4537A14
queue 3 maxrecevsize 7E0 pakhead 4C00264 paktail 4BFFB2C
queue 4 maxrecevsize 7E0 pakhead 46A629C paktail 46C2D00
queue 5 maxrecevsize 7E0 pakhead 4A1EBC4 paktail 4A2CF28
queue 6 maxrecevsize 7E0 pakhead 4BCEE48 paktail 4BEB8AC
queue 7 maxrecevsize 7E0 pakhead 4A66C6C paktail 4A57E34
queue 8 maxrecevsize 7E0 pakhead 4A6DD94 paktail 4A6E4CC
queue 9 maxrecevsize 7E0 pakhead 48A1420 paktail 48A1420
queue A maxrecevsize 7E0 pakhead 487FC98 paktail 4879EC0
queue B maxrecevsize 7E0 pakhead 4C09408 paktail 4C0CA2C
queue C maxrecevsize 7E0 pakhead 48AC004 paktail 48C16E8
queue D maxrecevsize 7E0 pakhead 489D91C paktail 48A0F40
queue E maxrecevsize 0 pakhead 0 paktail 0
queue F maxrecevsize 7E0 pakhead 486E8E0 paktail 486F3B4
Supervisor ASIC exception status
--------------------------------
Receive overrun 00000000 Transmit overrun 00000000
FrameSignatureErr 00000000 MicInitialize 00000002
BadFrameErr 00000000 LenExceededErr 00000000
BadJumboSegments 00000000
Supervisor ASIC Mic Registers
------------------------------
MicDirectPollInfo 80000200
MicIndicationsReceived 00000000
MicInterruptsReceived 00000001
MicPcsInfo 0000001F
MicPlbMasterConfiguration 00000000
MicRxFifosAvailable 00000000
MicRxFifosReady 0000BFFF
MicTimeOutPeriod: FrameTOPeriod: 00000EA6 DirectTOPeriod: 00004000
MicTransmFramesCopied 00000003
MicTxFifosAvailable 0000000E
MicConfiguration: Conf flag: 00000110 Interrupt Flag: 00000008
MicReceiveFifoAssignmen Queue 0 - 7: 33333333 Queue 8 - 15:33333333
MicReceiveFramesReady: FrameAvailable: 00000000 frameAvaiMask: 00000000
MicException:
Exception_flag 00000000
Message-1 00000000
Message-2 00000000
Message-3 00000000
MicIntRxFifo:
ReadPtr 00000780 WritePtr 00000780
WHeadPtr 00000780 TxFifoDepth C0000800
MicIntTxFifo:
ReadPtr 00000FA8 WritePtr 00000FA8
WHeadPtr 00000FA8 TxFifoDepth C0000800
MicDecodeInfo:
Fifo0: address: 03FF5000 asic_num: 00000100
Fifo1: address: 03FF4000 asic_num: 00000101
MicTransmitFifoInfo:
Fifo0: StartPtrs: 0E2C9000 ReadPtr: 0E2C9270
WritePtrs: 0E2C9270 Fifo_Flag: 8A800800
Weights: 001E001E
Fifo1: StartPtrs: 0E027400 ReadPtr: 0E027660
WritePtrs: 0E027660 Fifo_Flag: 89800400
Weights: 000A000A
MicReceiveFifoInfo:
Fifo0: StartPtr: 0E4AA000 ReadPtr: 0E4AAFA0
WritePtrs: 0E4AA000 Fifo_Flag: 8B000060
writeHeaderPtr: 0E4AA000
Fifo1: StartPtr: 0E786800 ReadPtr: 0E786808
WritePtrs: 0E786808 Fifo_Flag: 89800400
writeHeaderPtr: 0E786808
Fifo2: StartPtr: 0E73F000 ReadPtr: 0E73F000
WritePtrs: 0E73F000 Fifo_Flag: 89800400
writeHeaderPtr: 0E73F000
Fifo3: StartPtr: 0E99B800 ReadPtr: 0E99B8C8
WritePtrs: 0E99B8C8 Fifo_Flag: 89800400
writeHeaderPtr: 0E99B8C8
Fifo4: StartPtr: 0E7CE000 ReadPtr: 0E7CE000
WritePtrs: 0E7CE000 Fifo_Flag: 89800400
writeHeaderPtr: 0E7CE000
Fifo5: StartPtr: 0E87A600 ReadPtr: 0E87A600
WritePtrs: 0E87A600 Fifo_Flag: 88800200
writeHeaderPtr: 0E87A600
Fifo6: StartPtr: 0E951C00 ReadPtr: 0E951C00
WritePtrs: 0E951C00 Fifo_Flag: 89800400
writeHeaderPtr: 0E951C00
Fifo7: StartPtr: 0E8C1400 ReadPtr: 0E8C1738
WritePtrs: 0E8C1738 Fifo_Flag: 89800400
writeHeaderPtr: 0E8C1738
Fifo8: StartPtr: 0E92DE00 ReadPtr: 0E92DF10
WritePtrs: 0E92DF10 Fifo_Flag: 88800200
writeHeaderPtr: 0E92DF10
Fifo9: StartPtr: 0E2DB4D8 ReadPtr: 0E2DB4D8
WritePtrs: 0E2DB4D8 Fifo_Flag: 82800008
writeHeaderPtr: 0E2DB4D8
Fifo10: StartPtr: 0E817800 ReadPtr: 0E817860
WritePtrs: 0E817860 Fifo_Flag: 88800200
writeHeaderPtr: 0E817860
Fifo11: StartPtr: 0E2C8F00 ReadPtr: 0E2C8F00
WritePtrs: 0E2C8F00 Fifo_Flag: 86800080
writeHeaderPtr: 0E2C8F00
Fifo12: StartPtr: 0E844800 ReadPtr: 0E844B00
WritePtrs: 0E844800 Fifo_Flag: 89000100
writeHeaderPtr: 0E844800
Fifo13: StartPtr: 0E4A9E80 ReadPtr: 0E4A9E80
WritePtrs: 0E4A9E80 Fifo_Flag: 86800080
writeHeaderPtr: 0E4A9E80
Fifo14: StartPtr: 00000000 ReadPtr: 00000000
WritePtrs: 00000000 Fifo_Flag: 00800000
writeHeaderPtr: 00000000
Fifo15: StartPtr: 0E027940 ReadPtr: 0E027958
WritePtrs: 0E027958 Fifo_Flag: 84800020
writeHeaderPtr: 0E027958
===========================================================
Complete Board Id:0x0068
===========================================================
Switch# show controller cpu-interface
So, this command is all about queue-frames retrieved dropped by the CPU.
HTH
Reza
10-05-2012 04:39 PM
Thanks Reza.
I got the idea how we can use this command to determine number of packets currently in queues, dropped or processed by cpu. However I was puzzled by the term " cpu network interface ASIC and your example which also showed ASIC0.ASIC1 etc.
Thanks and have a great weekend.
10-06-2012 05:12 AM
Hello Sarah,
you are going very deep in your studies of TBSHOOT!
>> What is CPU network interface Asic? I am familiar with internal registers CPU uses to perform mathematical operation but what is CPU network interface?
This referes to the internal anatomy of a multilayer switch:
traffic arrives on external ports. The ports are divided in groups. Each group of port is managed by an ASIC chip that is specialized hardware. Each ASIC chip needs to interface to the main cpu in order to be able to send and receive packets that is to send packets that need to be process switched and to receive the responses from the main cpu.
So you can imagine a small internal network inside the switch that interconnects the ASICs that manage the port groups to the main cpu.
Another ASIC may act as front-end between port groups ASIC chips and the main cpu, so you get a cpu network interface ASIC.
My guess is that ASIC0, ASIC1 and so on are the port groups ASICs
Hope to help
Giuseppe
10-06-2012 11:02 AM
thanks Giuseppe
Have a great weekend.
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