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01-31-2019 01:37 AM - edited 03-08-2019 05:12 PM
Cisco CAT 9200, does it support non-blocking and where can I find information? It's not mentioned in the data sheet.
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01-31-2019 02:31 AM
Oversubscription to backplane is usually characteristic of modular switches with linecards and centralized forwarding (on sup), like cat4k, or Cat9400.
In fixed switches physical ports are reside and "served" directly by ASIC(s) on the switch. Of course, there are some intermediate components between physical ports and ASIC, but usually they don't have too much intelligence, and don't introduce "bottleneck".
So, main characteristic is ASIC performance. 9200 uses UADP 2.0 mini, which has up 100G total bandwidth.
I would assume, that for example in switch 9200-24T, two of such ASICs are used - 1 to serve access ports, and 1 to serve uplink ports. So, ideally architecture should be non-blocking.
If you need more details about architecture of the switch, I believe there are not too much places, where you can get it, apart of Cisco itself (TAC or account team) :-)
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01-31-2019 01:49 AM
Hello,
probably, you can use following resources
Table 8. Bandwidth Specifications
It's not mentioned explicitly, but we can do some calculation, for example:
Description | Switching capacity | Forwarding rate |
C9200-24T | 128 Gbps | 190.4 Mpps |
C9200-24T has 24x1G ports and 4x10G uplinks. So, total bandwidth would be: 24*2G (1g for ingress + 1g for egress) + 4*20G = 128Gbps, which matches switching capacity from the table.
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01-31-2019 02:08 AM
I understand this calculation, but non-blocking usually refers to the capacity available between the ports and the backplane.
For example, a set of 8* 1Gb ports should have 8* 1Gb (or 8* 2Gb for duplex) capacity to the backplane. Quite often this is not the case and this connectivity to the backplane is oversubscribed (e.g. 8 ports share 4 Gb connectivity to the backplane).
So the question is whether there is full capacity from the ports to the backplane.
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01-31-2019 02:31 AM
Oversubscription to backplane is usually characteristic of modular switches with linecards and centralized forwarding (on sup), like cat4k, or Cat9400.
In fixed switches physical ports are reside and "served" directly by ASIC(s) on the switch. Of course, there are some intermediate components between physical ports and ASIC, but usually they don't have too much intelligence, and don't introduce "bottleneck".
So, main characteristic is ASIC performance. 9200 uses UADP 2.0 mini, which has up 100G total bandwidth.
I would assume, that for example in switch 9200-24T, two of such ASICs are used - 1 to serve access ports, and 1 to serve uplink ports. So, ideally architecture should be non-blocking.
If you need more details about architecture of the switch, I believe there are not too much places, where you can get it, apart of Cisco itself (TAC or account team) :-)
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01-31-2019 02:38 AM
Just to add, I'm talking about standalone switch. If stack is planned, then bandwidth/oversubscription should be calculated accordingly, taking into account Stacking bandwidth limitation (160G), which probably might be exceeded under some circumstances (depends on model of stacking switches)
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01-31-2019 02:40 AM
Thanks for you reply, it was helpfull. We can continue now.
Regards,
Rick de Goeij
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06-03-2019 12:00 PM
Hello vb10,
I've the same doubt of this question.
Today, I have found the "Catalyst 9k e-book" that says Catalyst 9200 Switches Series have a single UADP 2.0 mini ASIC, in this case of non-mGig models (page 30).
The "Table Cisco UADP 2.0 , 2.0 XL and 2.0 mini comparison" on page 81 that talk about Cisco UADP 2.0 says that UADP 2.0 mini supports up to 80Gbps of inter-ASIC connectivity.
Please, you can access this document from the link below:
So, is it documment authentic?
The Catalyst 9200 and Catalyst 9200L Series switches have a nonblocking architecture?
Thank you very much for your comment and explanation!
Allyson
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01-31-2019 02:24 AM
The Catalyst 9200 is meant to be the "cheapest" switch (among the 9K family). Don't expect it to "compete" with the 9300 and this means that port buffers is the shallowest of the 9K range.
